1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Gabe Black
31 */
32
33#ifndef __CPU_O3_REGFILE_HH__
34#define __CPU_O3_REGFILE_HH__
35
36#include <vector>
37
38#include "arch/isa_traits.hh"
39#include "arch/kernel_stats.hh"
40#include "arch/types.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/o3/comm.hh"
44#include "debug/IEW.hh"
45
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Gabe Black
31 */
32
33#ifndef __CPU_O3_REGFILE_HH__
34#define __CPU_O3_REGFILE_HH__
35
36#include <vector>
37
38#include "arch/isa_traits.hh"
39#include "arch/kernel_stats.hh"
40#include "arch/types.hh"
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "cpu/o3/comm.hh"
44#include "debug/IEW.hh"
45
|
| 46class UnifiedFreeList;
47
|
46/**
47 * Simple physical register file class.
48 */
49class PhysRegFile
50{
51 private:
52
53 typedef TheISA::IntReg IntReg;
54 typedef TheISA::FloatReg FloatReg;
55 typedef TheISA::FloatRegBits FloatRegBits;
56
57 typedef union {
58 FloatReg d;
59 FloatRegBits q;
60 } PhysFloatReg;
61
62 /** Integer register file. */
| 48/**
49 * Simple physical register file class.
50 */
51class PhysRegFile
52{
53 private:
54
55 typedef TheISA::IntReg IntReg;
56 typedef TheISA::FloatReg FloatReg;
57 typedef TheISA::FloatRegBits FloatRegBits;
58
59 typedef union {
60 FloatReg d;
61 FloatRegBits q;
62 } PhysFloatReg;
63
64 /** Integer register file. */
|
63 IntReg *intRegFile;
| 65 std::vector<IntReg> intRegFile;
|
64
65 /** Floating point register file. */
| 66
67 /** Floating point register file. */
|
66 PhysFloatReg *floatRegFile;
| 68 std::vector<PhysFloatReg> floatRegFile;
|
67
68 /**
69 * The first floating-point physical register index. The physical
70 * register file has a single continuous index space, with the
71 * initial indices mapping to the integer registers, followed
72 * immediately by the floating-point registers. Thus the first
73 * floating-point index is equal to the number of integer
74 * registers.
| 69
70 /**
71 * The first floating-point physical register index. The physical
72 * register file has a single continuous index space, with the
73 * initial indices mapping to the integer registers, followed
74 * immediately by the floating-point registers. Thus the first
75 * floating-point index is equal to the number of integer
76 * registers.
|
| 77 *
78 * Note that this internal organizational detail on how physical
79 * register file indices are ordered should *NOT* be exposed
80 * outside of this class. Other classes can use the is*PhysReg()
81 * methods to map from a physical register index to a class
82 * without knowing the internal structure of the index map.
|
75 */
76 unsigned baseFloatRegIndex;
77
78 /** Total number of physical registers. */
79 unsigned totalNumRegs;
80
81 public:
82 /**
83 * Constructs a physical register file with the specified amount of
84 * integer and floating point registers.
85 */
86 PhysRegFile(unsigned _numPhysicalIntRegs,
87 unsigned _numPhysicalFloatRegs);
88
89 /**
90 * Destructor to free resources
91 */
| 83 */
84 unsigned baseFloatRegIndex;
85
86 /** Total number of physical registers. */
87 unsigned totalNumRegs;
88
89 public:
90 /**
91 * Constructs a physical register file with the specified amount of
92 * integer and floating point registers.
93 */
94 PhysRegFile(unsigned _numPhysicalIntRegs,
95 unsigned _numPhysicalFloatRegs);
96
97 /**
98 * Destructor to free resources
99 */
|
92 ~PhysRegFile();
| 100 ~PhysRegFile() {}
|
93
| 101
|
| 102 /** Initialize the free list */
103 void initFreeList(UnifiedFreeList *freeList);
104
|
94 /** @return the number of integer physical registers. */
95 unsigned numIntPhysRegs() const { return baseFloatRegIndex; }
96
97 /** @return the number of floating-point physical registers. */
98 unsigned numFloatPhysRegs() const
99 { return totalNumRegs - baseFloatRegIndex; }
100
101 /** @return the total number of physical registers. */
102 unsigned totalNumPhysRegs() const { return totalNumRegs; }
103
104 /**
105 * @return true if the specified physical register index
106 * corresponds to an integer physical register.
107 */
108 bool isIntPhysReg(PhysRegIndex reg_idx) const
109 {
110 return 0 <= reg_idx && reg_idx < baseFloatRegIndex;
111 }
112
113 /**
114 * @return true if the specified physical register index
115 * corresponds to a floating-point physical register.
116 */
117 bool isFloatPhysReg(PhysRegIndex reg_idx) const
118 {
119 return (baseFloatRegIndex <= reg_idx && reg_idx < totalNumRegs);
120 }
121
122 /** Reads an integer register. */
123 uint64_t readIntReg(PhysRegIndex reg_idx) const
124 {
125 assert(isIntPhysReg(reg_idx));
126
127 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
128 "%#x\n", int(reg_idx), intRegFile[reg_idx]);
129 return intRegFile[reg_idx];
130 }
131
132 /** Reads a floating point register (double precision). */
133 FloatReg readFloatReg(PhysRegIndex reg_idx) const
134 {
135 assert(isFloatPhysReg(reg_idx));
136
137 // Remove the base Float reg dependency.
138 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
139
140 DPRINTF(IEW, "RegFile: Access to float register %i, has "
141 "data %#x\n", int(reg_idx), floatRegFile[reg_offset].q);
142
143 return floatRegFile[reg_offset].d;
144 }
145
146 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) const
147 {
148 assert(isFloatPhysReg(reg_idx));
149
150 // Remove the base Float reg dependency.
151 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
152
153 FloatRegBits floatRegBits = floatRegFile[reg_offset].q;
154
155 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
156 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
157
158 return floatRegBits;
159 }
160
161 /** Sets an integer register to the given value. */
162 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
163 {
164 assert(isIntPhysReg(reg_idx));
165
166 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
167 int(reg_idx), val);
168
169 if (reg_idx != TheISA::ZeroReg)
170 intRegFile[reg_idx] = val;
171 }
172
173 /** Sets a double precision floating point register to the given value. */
174 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
175 {
176 assert(isFloatPhysReg(reg_idx));
177
178 // Remove the base Float reg dependency.
179 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
180
181 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
182 int(reg_idx), (uint64_t)val);
183
184#if THE_ISA == ALPHA_ISA
185 if (reg_offset != TheISA::ZeroReg)
186#endif
187 floatRegFile[reg_offset].d = val;
188 }
189
190 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
191 {
192 assert(isFloatPhysReg(reg_idx));
193
194 // Remove the base Float reg dependency.
195 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
196
197 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
198 int(reg_idx), (uint64_t)val);
199
200 floatRegFile[reg_offset].q = val;
201 }
202
203};
204
205
| 105 /** @return the number of integer physical registers. */
106 unsigned numIntPhysRegs() const { return baseFloatRegIndex; }
107
108 /** @return the number of floating-point physical registers. */
109 unsigned numFloatPhysRegs() const
110 { return totalNumRegs - baseFloatRegIndex; }
111
112 /** @return the total number of physical registers. */
113 unsigned totalNumPhysRegs() const { return totalNumRegs; }
114
115 /**
116 * @return true if the specified physical register index
117 * corresponds to an integer physical register.
118 */
119 bool isIntPhysReg(PhysRegIndex reg_idx) const
120 {
121 return 0 <= reg_idx && reg_idx < baseFloatRegIndex;
122 }
123
124 /**
125 * @return true if the specified physical register index
126 * corresponds to a floating-point physical register.
127 */
128 bool isFloatPhysReg(PhysRegIndex reg_idx) const
129 {
130 return (baseFloatRegIndex <= reg_idx && reg_idx < totalNumRegs);
131 }
132
133 /** Reads an integer register. */
134 uint64_t readIntReg(PhysRegIndex reg_idx) const
135 {
136 assert(isIntPhysReg(reg_idx));
137
138 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
139 "%#x\n", int(reg_idx), intRegFile[reg_idx]);
140 return intRegFile[reg_idx];
141 }
142
143 /** Reads a floating point register (double precision). */
144 FloatReg readFloatReg(PhysRegIndex reg_idx) const
145 {
146 assert(isFloatPhysReg(reg_idx));
147
148 // Remove the base Float reg dependency.
149 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
150
151 DPRINTF(IEW, "RegFile: Access to float register %i, has "
152 "data %#x\n", int(reg_idx), floatRegFile[reg_offset].q);
153
154 return floatRegFile[reg_offset].d;
155 }
156
157 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) const
158 {
159 assert(isFloatPhysReg(reg_idx));
160
161 // Remove the base Float reg dependency.
162 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
163
164 FloatRegBits floatRegBits = floatRegFile[reg_offset].q;
165
166 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
167 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
168
169 return floatRegBits;
170 }
171
172 /** Sets an integer register to the given value. */
173 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
174 {
175 assert(isIntPhysReg(reg_idx));
176
177 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
178 int(reg_idx), val);
179
180 if (reg_idx != TheISA::ZeroReg)
181 intRegFile[reg_idx] = val;
182 }
183
184 /** Sets a double precision floating point register to the given value. */
185 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
186 {
187 assert(isFloatPhysReg(reg_idx));
188
189 // Remove the base Float reg dependency.
190 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
191
192 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
193 int(reg_idx), (uint64_t)val);
194
195#if THE_ISA == ALPHA_ISA
196 if (reg_offset != TheISA::ZeroReg)
197#endif
198 floatRegFile[reg_offset].d = val;
199 }
200
201 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
202 {
203 assert(isFloatPhysReg(reg_idx));
204
205 // Remove the base Float reg dependency.
206 PhysRegIndex reg_offset = reg_idx - baseFloatRegIndex;
207
208 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
209 int(reg_idx), (uint64_t)val);
210
211 floatRegFile[reg_offset].q = val;
212 }
213
214};
215
216
|
206inline
207PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
208 unsigned _numPhysicalFloatRegs)
209 : baseFloatRegIndex(_numPhysicalIntRegs),
210 totalNumRegs(_numPhysicalIntRegs + _numPhysicalFloatRegs)
211{
212 intRegFile = new IntReg[_numPhysicalIntRegs];
213 floatRegFile = new PhysFloatReg[_numPhysicalFloatRegs];
214
215 memset(intRegFile, 0, sizeof(IntReg) * _numPhysicalIntRegs);
216 memset(floatRegFile, 0, sizeof(PhysFloatReg) * _numPhysicalFloatRegs);
217}
218
219
220inline
221PhysRegFile::~PhysRegFile()
222{
223 delete intRegFile;
224 delete floatRegFile;
225}
226
| |
227#endif //__CPU_O3_REGFILE_HH__
| 217#endif //__CPU_O3_REGFILE_HH__
|