1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 * 28 * Authors: Kevin Lim 29 * Gabe Black
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27 */ 28
| 30 */ 31
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29#ifndef __CPU_O3_REGFILE_HH__ 30#define __CPU_O3_REGFILE_HH__
| 32#ifndef __CPU_O3_CPU_REGFILE_HH__ 33#define __CPU_O3_CPU_REGFILE_HH__
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31
| 34
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| 35// @todo: Destructor 36
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32#include "arch/isa_traits.hh" 33#include "arch/faults.hh" 34#include "base/trace.hh" 35#include "config/full_system.hh" 36#include "cpu/o3/comm.hh" 37 38#if FULL_SYSTEM 39#include "kern/kernel_stats.hh" 40 41#endif 42
| 37#include "arch/isa_traits.hh" 38#include "arch/faults.hh" 39#include "base/trace.hh" 40#include "config/full_system.hh" 41#include "cpu/o3/comm.hh" 42 43#if FULL_SYSTEM 44#include "kern/kernel_stats.hh" 45 46#endif 47
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43#include <vector>
| 48// This really only depends on the ISA, and not the Impl. It might be nicer 49// to see if I can make it depend on nothing... 50// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA, 51// and should go in the AlphaFullCPU.
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44
| 52
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45/** 46 * Simple physical register file class. 47 * This really only depends on the ISA, and not the Impl. Things that are 48 * in the ifdef FULL_SYSTEM are pretty dependent on the ISA, and probably 49 * should go in the AlphaFullCPU. 50 */
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51template <class Impl> 52class PhysRegFile 53{ 54 protected: 55 typedef TheISA::IntReg IntReg; 56 typedef TheISA::FloatReg FloatReg; 57 typedef TheISA::MiscRegFile MiscRegFile; 58 typedef TheISA::MiscReg MiscReg;
| 53template <class Impl> 54class PhysRegFile 55{ 56 protected: 57 typedef TheISA::IntReg IntReg; 58 typedef TheISA::FloatReg FloatReg; 59 typedef TheISA::MiscRegFile MiscRegFile; 60 typedef TheISA::MiscReg MiscReg;
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59 // Note that most of the definitions of the IntReg, FloatReg, etc. exist 60 // within the Impl/ISA class and not within this PhysRegFile class.
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61
| 61
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62 // Will make these registers public for now, but they probably should 63 // be private eventually with some accessor functions.
| 62 //Note that most of the definitions of the IntReg, FloatReg, etc. exist 63 //within the Impl/ISA class and not within this PhysRegFile class. 64 65 //Will need some way to allow stuff like swap_palshadow to access the 66 //correct registers. Might require code changes to swap_palshadow and 67 //other execution contexts. 68 69 //Will make these registers public for now, but they probably should 70 //be private eventually with some accessor functions.
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64 public: 65 typedef typename Impl::FullCPU FullCPU; 66
| 71 public: 72 typedef typename Impl::FullCPU FullCPU; 73
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67 /** 68 * Constructs a physical register file with the specified amount of 69 * integer and floating point registers. 70 */
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71 PhysRegFile(unsigned _numPhysicalIntRegs, 72 unsigned _numPhysicalFloatRegs); 73 74 //Everything below should be pretty well identical to the normal 75 //register file that exists within AlphaISA class. 76 //The duplication is unfortunate but it's better than having 77 //different ways to access certain registers. 78 79 //Add these in later when everything else is in place 80// void serialize(std::ostream &os); 81// void unserialize(Checkpoint *cp, const std::string §ion); 82
| 74 PhysRegFile(unsigned _numPhysicalIntRegs, 75 unsigned _numPhysicalFloatRegs); 76 77 //Everything below should be pretty well identical to the normal 78 //register file that exists within AlphaISA class. 79 //The duplication is unfortunate but it's better than having 80 //different ways to access certain registers. 81 82 //Add these in later when everything else is in place 83// void serialize(std::ostream &os); 84// void unserialize(Checkpoint *cp, const std::string §ion); 85
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83 /** Reads an integer register. */
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84 uint64_t readIntReg(PhysRegIndex reg_idx) 85 { 86 assert(reg_idx < numPhysicalIntRegs); 87 88 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 89 "%i\n", int(reg_idx), intRegFile[reg_idx]); 90 return intRegFile[reg_idx]; 91 } 92 93 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 94 { 95 // Remove the base Float reg dependency. 96 reg_idx = reg_idx - numPhysicalIntRegs; 97 98 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 99 100 FloatReg floatReg = floatRegFile.readReg(reg_idx, width); 101 102 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 103 "data %8.8d\n", int(reg_idx), (double)floatReg); 104 105 return floatReg; 106 } 107
| 86 uint64_t readIntReg(PhysRegIndex reg_idx) 87 { 88 assert(reg_idx < numPhysicalIntRegs); 89 90 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 91 "%i\n", int(reg_idx), intRegFile[reg_idx]); 92 return intRegFile[reg_idx]; 93 } 94 95 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 96 { 97 // Remove the base Float reg dependency. 98 reg_idx = reg_idx - numPhysicalIntRegs; 99 100 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 101 102 FloatReg floatReg = floatRegFile.readReg(reg_idx, width); 103 104 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 105 "data %8.8d\n", int(reg_idx), (double)floatReg); 106 107 return floatReg; 108 } 109
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108 /** Reads a floating point register (double precision). */
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109 FloatReg readFloatReg(PhysRegIndex reg_idx) 110 { 111 // Remove the base Float reg dependency. 112 reg_idx = reg_idx - numPhysicalIntRegs; 113 114 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 115 116 FloatReg floatReg = floatRegFile.readReg(reg_idx); 117 118 DPRINTF(IEW, "RegFile: Access to float register %i, has " 119 "data %8.8d\n", int(reg_idx), (double)floatReg); 120 121 return floatReg; 122 } 123
| 110 FloatReg readFloatReg(PhysRegIndex reg_idx) 111 { 112 // Remove the base Float reg dependency. 113 reg_idx = reg_idx - numPhysicalIntRegs; 114 115 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 116 117 FloatReg floatReg = floatRegFile.readReg(reg_idx); 118 119 DPRINTF(IEW, "RegFile: Access to float register %i, has " 120 "data %8.8d\n", int(reg_idx), (double)floatReg); 121 122 return floatReg; 123 } 124
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124 /** Reads a floating point register as an integer. */
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125 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 126 { 127 // Remove the base Float reg dependency. 128 reg_idx = reg_idx - numPhysicalIntRegs; 129 130 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 131 132 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width); 133 134 DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 135 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 136 137 return floatRegBits; 138 } 139 140 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 141 { 142 // Remove the base Float reg dependency. 143 reg_idx = reg_idx - numPhysicalIntRegs; 144 145 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 146 147 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx); 148 149 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 150 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 151 152 return floatRegBits; 153 } 154
| 125 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 126 { 127 // Remove the base Float reg dependency. 128 reg_idx = reg_idx - numPhysicalIntRegs; 129 130 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 131 132 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width); 133 134 DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, " 135 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 136 137 return floatRegBits; 138 } 139 140 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 141 { 142 // Remove the base Float reg dependency. 143 reg_idx = reg_idx - numPhysicalIntRegs; 144 145 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 146 147 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx); 148 149 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 150 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits); 151 152 return floatRegBits; 153 } 154
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155 /** Sets an integer register to the given value. */
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156 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 157 { 158 assert(reg_idx < numPhysicalIntRegs); 159 160 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 161 int(reg_idx), val); 162
| 155 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 156 { 157 assert(reg_idx < numPhysicalIntRegs); 158 159 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n", 160 int(reg_idx), val); 161
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163 if (reg_idx != TheISA::ZeroReg) 164 intRegFile[reg_idx] = val;
| 162 intRegFile[reg_idx] = val;
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165 } 166
| 163 } 164
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167 /** Sets a single precision floating point register to the given value. */
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168 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 169 { 170 // Remove the base Float reg dependency. 171 reg_idx = reg_idx - numPhysicalIntRegs; 172 173 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 174 175 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 176 int(reg_idx), (double)val); 177
| 165 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 166 { 167 // Remove the base Float reg dependency. 168 reg_idx = reg_idx - numPhysicalIntRegs; 169 170 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 171 172 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 173 int(reg_idx), (double)val); 174
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178 if (reg_idx != TheISA::ZeroReg) 179 floatRegFile.setReg(reg_idx, val, width);
| 175 floatRegFile.setReg(reg_idx, val, width);
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180 } 181
| 176 } 177
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182 /** Sets a double precision floating point register to the given value. */
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183 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 184 { 185 // Remove the base Float reg dependency. 186 reg_idx = reg_idx - numPhysicalIntRegs; 187 188 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 189 190 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 191 int(reg_idx), (double)val); 192
| 178 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 179 { 180 // Remove the base Float reg dependency. 181 reg_idx = reg_idx - numPhysicalIntRegs; 182 183 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 184 185 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n", 186 int(reg_idx), (double)val); 187
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193 if (reg_idx != TheISA::ZeroReg) 194 floatRegFile.setReg(reg_idx, val);
| 188 floatRegFile.setReg(reg_idx, val);
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195 } 196
| 189 } 190
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197 /** Sets a floating point register to the given integer value. */
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198 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 199 { 200 // Remove the base Float reg dependency. 201 reg_idx = reg_idx - numPhysicalIntRegs; 202 203 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 204 205 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 206 int(reg_idx), (uint64_t)val); 207 208 floatRegFile.setRegBits(reg_idx, val, width); 209 } 210 211 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 212 { 213 // Remove the base Float reg dependency. 214 reg_idx = reg_idx - numPhysicalIntRegs; 215 216 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 217 218 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 219 int(reg_idx), (uint64_t)val);
| 191 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 192 { 193 // Remove the base Float reg dependency. 194 reg_idx = reg_idx - numPhysicalIntRegs; 195 196 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 197 198 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 199 int(reg_idx), (uint64_t)val); 200 201 floatRegFile.setRegBits(reg_idx, val, width); 202 } 203 204 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 205 { 206 // Remove the base Float reg dependency. 207 reg_idx = reg_idx - numPhysicalIntRegs; 208 209 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 210 211 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", 212 int(reg_idx), (uint64_t)val);
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| 213 214 floatRegFile.setRegBits(reg_idx, val);
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220 } 221
| 215 } 216
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222 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, 223 unsigned thread_id)
| 217 uint64_t readPC()
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224 {
| 218 {
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225 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, 226 cpu->xcBase(thread_id));
| 219 return pc;
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227 } 228
| 220 } 221
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229 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
| 222 void setPC(uint64_t val)
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230 {
| 223 {
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231 return miscRegs[thread_id].setReg(misc_reg, val);
| 224 pc = val;
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232 } 233
| 225 } 226
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234 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, 235 unsigned thread_id)
| 227 void setNextPC(uint64_t val)
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236 {
| 228 {
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237 return miscRegs[thread_id].setRegWithEffect(misc_reg, val, 238 cpu->xcBase(thread_id));
| 229 npc = val;
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239 } 240
| 230 } 231
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| 232 //Consider leaving this stuff and below in some implementation specific 233 //file as opposed to the general register file. Or have a derived class. 234 MiscReg readMiscReg(int misc_reg) 235 { 236 // Dummy function for now. 237 // @todo: Fix this once proxy XC is used. 238 return 0; 239 } 240 241 Fault setMiscReg(int misc_reg, const MiscReg &val) 242 { 243 // Dummy function for now. 244 // @todo: Fix this once proxy XC is used. 245 return NoFault; 246 } 247
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241#if FULL_SYSTEM 242 int readIntrFlag() { return intrflag; }
| 248#if FULL_SYSTEM 249 int readIntrFlag() { return intrflag; }
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243 /** Sets an interrupt flag. */
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244 void setIntrFlag(int val) { intrflag = val; } 245#endif 246
| 250 void setIntrFlag(int val) { intrflag = val; } 251#endif 252
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| 253 // These should be private eventually, but will be public for now 254 // so that I can hack around the initregs issue.
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247 public: 248 /** (signed) integer register file. */
| 255 public: 256 /** (signed) integer register file. */
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249 std::vector<IntReg> intRegFile;
| 257 IntReg *intRegFile;
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250 251 /** Floating point register file. */
| 258 259 /** Floating point register file. */
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252 std::vector<FloatReg> floatRegFile;
| 260 FloatReg *floatRegFile;
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253 254 /** Miscellaneous register file. */
| 261 262 /** Miscellaneous register file. */
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255 MiscRegFile miscRegs[Impl::MaxThreads];
| 263 MiscRegFile miscRegs;
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256
| 264
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| 265 /** Program counter. */ 266 Addr pc; 267 268 /** Next-cycle program counter. */ 269 Addr npc; 270
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257#if FULL_SYSTEM 258 private:
| 271#if FULL_SYSTEM 272 private:
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| 273 // This is ISA specifc stuff; remove it eventually once ISAImpl is used 274// IntReg palregs[NumIntRegs]; // PAL shadow registers
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259 int intrflag; // interrupt flag
| 275 int intrflag; // interrupt flag
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| 276 bool pal_shadow; // using pal_shadow registers
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260#endif 261 262 private:
| 277#endif 278 279 private:
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263 /** CPU pointer. */
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264 FullCPU *cpu; 265 266 public:
| 280 FullCPU *cpu; 281 282 public:
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267 /** Sets the CPU pointer. */
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268 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 269
| 283 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } 284
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270 /** Number of physical integer registers. */
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271 unsigned numPhysicalIntRegs;
| 285 unsigned numPhysicalIntRegs;
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272 /** Number of physical floating point registers. */
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273 unsigned numPhysicalFloatRegs; 274}; 275 276template <class Impl> 277PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 278 unsigned _numPhysicalFloatRegs) 279 : numPhysicalIntRegs(_numPhysicalIntRegs), 280 numPhysicalFloatRegs(_numPhysicalFloatRegs) 281{
| 286 unsigned numPhysicalFloatRegs; 287}; 288 289template <class Impl> 290PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 291 unsigned _numPhysicalFloatRegs) 292 : numPhysicalIntRegs(_numPhysicalIntRegs), 293 numPhysicalFloatRegs(_numPhysicalFloatRegs) 294{
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282 intRegFile.resize(numPhysicalIntRegs); 283 floatRegFile.resize(numPhysicalFloatRegs);
| 295 intRegFile = new IntReg[numPhysicalIntRegs]; 296 floatRegFile = new FloatReg[numPhysicalFloatRegs];
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284
| 297
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285 //memset(intRegFile, 0, sizeof(*intRegFile)); 286 //memset(floatRegFile, 0, sizeof(*floatRegFile));
| 298 memset(intRegFile, 0, sizeof(*intRegFile)); 299 memset(floatRegFile, 0, sizeof(*floatRegFile));
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287} 288
| 300} 301
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289#endif
| 302#endif // __CPU_O3_CPU_REGFILE_HH__
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| |