3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Gabe Black
43 */
44
45#ifndef __CPU_O3_REGFILE_HH__
46#define __CPU_O3_REGFILE_HH__
47
48#include <vector>
49
50#include "arch/isa_traits.hh"
51#include "arch/types.hh"
52#include "base/trace.hh"
53#include "config/the_isa.hh"
54#include "cpu/o3/comm.hh"
55#include "debug/IEW.hh"
56#include "enums/VecRegRenameMode.hh"
57
58class UnifiedFreeList;
59
60/**
61 * Simple physical register file class.
62 */
63class PhysRegFile
64{
65 private:
66
67 using VecElem = TheISA::VecElem;
68 using VecRegContainer = TheISA::VecRegContainer;
69 using PhysIds = std::vector<PhysRegId>;
70 using VecMode = Enums::VecRegRenameMode;
71 using VecPredRegContainer = TheISA::VecPredRegContainer;
72 public:
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Gabe Black
43 */
44
45#ifndef __CPU_O3_REGFILE_HH__
46#define __CPU_O3_REGFILE_HH__
47
48#include <vector>
49
50#include "arch/isa_traits.hh"
51#include "arch/types.hh"
52#include "base/trace.hh"
53#include "config/the_isa.hh"
54#include "cpu/o3/comm.hh"
55#include "debug/IEW.hh"
56#include "enums/VecRegRenameMode.hh"
57
58class UnifiedFreeList;
59
60/**
61 * Simple physical register file class.
62 */
63class PhysRegFile
64{
65 private:
66
67 using VecElem = TheISA::VecElem;
68 using VecRegContainer = TheISA::VecRegContainer;
69 using PhysIds = std::vector<PhysRegId>;
70 using VecMode = Enums::VecRegRenameMode;
71 using VecPredRegContainer = TheISA::VecPredRegContainer;
72 public:
|
75 private:
76 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
77
78 /** Integer register file. */
79 std::vector<RegVal> intRegFile;
80 std::vector<PhysRegId> intRegIds;
81
82 /** Floating point register file. */
83 std::vector<RegVal> floatRegFile;
84 std::vector<PhysRegId> floatRegIds;
85
86 /** Vector register file. */
87 std::vector<VecRegContainer> vectorRegFile;
88 std::vector<PhysRegId> vecRegIds;
89 std::vector<PhysRegId> vecElemIds;
90
91 /** Predicate register file. */
92 std::vector<VecPredRegContainer> vecPredRegFile;
93 std::vector<PhysRegId> vecPredRegIds;
94
95 /** Condition-code register file. */
96 std::vector<RegVal> ccRegFile;
97 std::vector<PhysRegId> ccRegIds;
98
99 /** Misc Reg Ids */
100 std::vector<PhysRegId> miscRegIds;
101
102 /**
103 * Number of physical general purpose registers
104 */
105 unsigned numPhysicalIntRegs;
106
107 /**
108 * Number of physical floating point registers
109 */
110 unsigned numPhysicalFloatRegs;
111
112 /**
113 * Number of physical vector registers
114 */
115 unsigned numPhysicalVecRegs;
116
117 /**
118 * Number of physical vector element registers
119 */
120 unsigned numPhysicalVecElemRegs;
121
122 /**
123 * Number of physical predicate registers
124 */
125 unsigned numPhysicalVecPredRegs;
126
127 /**
128 * Number of physical CC registers
129 */
130 unsigned numPhysicalCCRegs;
131
132 /** Total number of physical registers. */
133 unsigned totalNumRegs;
134
135 /** Mode in which vector registers are addressed. */
136 VecMode vecMode;
137
138 public:
139 /**
140 * Constructs a physical register file with the specified amount of
141 * integer and floating point registers.
142 */
143 PhysRegFile(unsigned _numPhysicalIntRegs,
144 unsigned _numPhysicalFloatRegs,
145 unsigned _numPhysicalVecRegs,
146 unsigned _numPhysicalVecPredRegs,
147 unsigned _numPhysicalCCRegs,
148 VecMode vmode
149 );
150
151 /**
152 * Destructor to free resources
153 */
154 ~PhysRegFile() {}
155
156 /** Initialize the free list */
157 void initFreeList(UnifiedFreeList *freeList);
158
159 /** @return the number of integer physical registers. */
160 unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
161
162 /** @return the number of floating-point physical registers. */
163 unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
164 /** @return the number of vector physical registers. */
165 unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
166 /** @return the number of predicate physical registers. */
167 unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
168
169 /** @return the number of vector physical registers. */
170 unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
171
172 /** @return the number of condition-code physical registers. */
173 unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
174
175 /** @return the total number of physical registers. */
176 unsigned totalNumPhysRegs() const { return totalNumRegs; }
177
178 /** Gets a misc register PhysRegIdPtr. */
179 PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
180 return &miscRegIds[reg_idx];
181 }
182
183 /** Reads an integer register. */
184 RegVal
185 readIntReg(PhysRegIdPtr phys_reg) const
186 {
187 assert(phys_reg->isIntPhysReg());
188
189 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
190 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
191 return intRegFile[phys_reg->index()];
192 }
193
194 RegVal
195 readFloatReg(PhysRegIdPtr phys_reg) const
196 {
197 assert(phys_reg->isFloatPhysReg());
198
199 RegVal floatRegBits = floatRegFile[phys_reg->index()];
200
201 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
202 "has data %#x\n", phys_reg->index(), floatRegBits);
203
204 return floatRegBits;
205 }
206
207 /** Reads a vector register. */
208 const VecRegContainer &
209 readVecReg(PhysRegIdPtr phys_reg) const
210 {
211 assert(phys_reg->isVectorPhysReg());
212
213 DPRINTF(IEW, "RegFile: Access to vector register %i, has "
214 "data %s\n", int(phys_reg->index()),
215 vectorRegFile[phys_reg->index()].print());
216
217 return vectorRegFile[phys_reg->index()];
218 }
219
220 /** Reads a vector register for modification. */
221 VecRegContainer &
222 getWritableVecReg(PhysRegIdPtr phys_reg)
223 {
224 /* const_cast for not duplicating code above. */
225 return const_cast<VecRegContainer&>(readVecReg(phys_reg));
226 }
227
228 /** Reads a vector register lane. */
229 template <typename VecElem, int LaneIdx>
230 VecLaneT<VecElem, true>
231 readVecLane(PhysRegIdPtr phys_reg) const
232 {
233 return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
234 }
235
236 /** Reads a vector register lane. */
237 template <typename VecElem>
238 VecLaneT<VecElem, true>
239 readVecLane(PhysRegIdPtr phys_reg) const
240 {
241 return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
242 }
243
244 /** Get a vector register lane for modification. */
245 template <typename LD>
246 void
247 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
248 {
249 assert(phys_reg->isVectorPhysReg());
250
251 DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
252 int(phys_reg->index()), phys_reg->elemIndex(), val);
253
254 vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
255 phys_reg->elemIndex()) = val;
256 }
257
258 /** Reads a vector element. */
259 const VecElem &
260 readVecElem(PhysRegIdPtr phys_reg) const
261 {
262 assert(phys_reg->isVectorPhysElem());
263 auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
264 const VecElem& val = ret[phys_reg->elemIndex()];
265 DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
266 " has data %#x\n", phys_reg->elemIndex(),
267 int(phys_reg->index()), val);
268
269 return val;
270 }
271
272 /** Reads a predicate register. */
273 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
274 {
275 assert(phys_reg->isVecPredPhysReg());
276
277 DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
278 "data %s\n", int(phys_reg->index()),
279 vecPredRegFile[phys_reg->index()].print());
280
281 return vecPredRegFile[phys_reg->index()];
282 }
283
284 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
285 {
286 /* const_cast for not duplicating code above. */
287 return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
288 }
289
290 /** Reads a condition-code register. */
291 RegVal
292 readCCReg(PhysRegIdPtr phys_reg)
293 {
294 assert(phys_reg->isCCPhysReg());
295
296 DPRINTF(IEW, "RegFile: Access to cc register %i, has "
297 "data %#x\n", phys_reg->index(),
298 ccRegFile[phys_reg->index()]);
299
300 return ccRegFile[phys_reg->index()];
301 }
302
303 /** Sets an integer register to the given value. */
304 void
305 setIntReg(PhysRegIdPtr phys_reg, RegVal val)
306 {
307 assert(phys_reg->isIntPhysReg());
308
309 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
310 phys_reg->index(), val);
311
312 if (!phys_reg->isZeroReg())
313 intRegFile[phys_reg->index()] = val;
314 }
315
316 void
317 setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
318 {
319 assert(phys_reg->isFloatPhysReg());
320
321 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
322 phys_reg->index(), (uint64_t)val);
323
324 if (!phys_reg->isZeroReg())
325 floatRegFile[phys_reg->index()] = val;
326 }
327
328 /** Sets a vector register to the given value. */
329 void
330 setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
331 {
332 assert(phys_reg->isVectorPhysReg());
333
334 DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
335 int(phys_reg->index()), val.print());
336
337 vectorRegFile[phys_reg->index()] = val;
338 }
339
340 /** Sets a vector register to the given value. */
341 void
342 setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
343 {
344 assert(phys_reg->isVectorPhysElem());
345
346 DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
347 " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
348
349 vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
350 val;
351 }
352
353 /** Sets a predicate register to the given value. */
354 void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
355 {
356 assert(phys_reg->isVecPredPhysReg());
357
358 DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
359 int(phys_reg->index()), val.print());
360
361 vecPredRegFile[phys_reg->index()] = val;
362 }
363
364 /** Sets a condition-code register to the given value. */
365 void
366 setCCReg(PhysRegIdPtr phys_reg, RegVal val)
367 {
368 assert(phys_reg->isCCPhysReg());
369
370 DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
371 phys_reg->index(), (uint64_t)val);
372
373 ccRegFile[phys_reg->index()] = val;
374 }
375
376 /** Get the PhysRegIds of the elems of a vector register.
377 * Auxiliary function to transition from Full vector mode to Elem mode.
378 */
379 IdRange getRegElemIds(PhysRegIdPtr reg);
380
381 /**
382 * Get the PhysRegIds of the elems of all vector registers.
383 * Auxiliary function to transition from Full vector mode to Elem mode
384 * and to initialise the rename map.
385 */
386 IdRange getRegIds(RegClass cls);
387
388 /**
389 * Get the true physical register id.
390 * As many parts work with PhysRegIdPtr, we need to be able to produce
391 * the pointer out of just class and register idx.
392 */
393 PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
394};
395
396
397#endif //__CPU_O3_REGFILE_HH__
| 75 private:
76 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
77
78 /** Integer register file. */
79 std::vector<RegVal> intRegFile;
80 std::vector<PhysRegId> intRegIds;
81
82 /** Floating point register file. */
83 std::vector<RegVal> floatRegFile;
84 std::vector<PhysRegId> floatRegIds;
85
86 /** Vector register file. */
87 std::vector<VecRegContainer> vectorRegFile;
88 std::vector<PhysRegId> vecRegIds;
89 std::vector<PhysRegId> vecElemIds;
90
91 /** Predicate register file. */
92 std::vector<VecPredRegContainer> vecPredRegFile;
93 std::vector<PhysRegId> vecPredRegIds;
94
95 /** Condition-code register file. */
96 std::vector<RegVal> ccRegFile;
97 std::vector<PhysRegId> ccRegIds;
98
99 /** Misc Reg Ids */
100 std::vector<PhysRegId> miscRegIds;
101
102 /**
103 * Number of physical general purpose registers
104 */
105 unsigned numPhysicalIntRegs;
106
107 /**
108 * Number of physical floating point registers
109 */
110 unsigned numPhysicalFloatRegs;
111
112 /**
113 * Number of physical vector registers
114 */
115 unsigned numPhysicalVecRegs;
116
117 /**
118 * Number of physical vector element registers
119 */
120 unsigned numPhysicalVecElemRegs;
121
122 /**
123 * Number of physical predicate registers
124 */
125 unsigned numPhysicalVecPredRegs;
126
127 /**
128 * Number of physical CC registers
129 */
130 unsigned numPhysicalCCRegs;
131
132 /** Total number of physical registers. */
133 unsigned totalNumRegs;
134
135 /** Mode in which vector registers are addressed. */
136 VecMode vecMode;
137
138 public:
139 /**
140 * Constructs a physical register file with the specified amount of
141 * integer and floating point registers.
142 */
143 PhysRegFile(unsigned _numPhysicalIntRegs,
144 unsigned _numPhysicalFloatRegs,
145 unsigned _numPhysicalVecRegs,
146 unsigned _numPhysicalVecPredRegs,
147 unsigned _numPhysicalCCRegs,
148 VecMode vmode
149 );
150
151 /**
152 * Destructor to free resources
153 */
154 ~PhysRegFile() {}
155
156 /** Initialize the free list */
157 void initFreeList(UnifiedFreeList *freeList);
158
159 /** @return the number of integer physical registers. */
160 unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
161
162 /** @return the number of floating-point physical registers. */
163 unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
164 /** @return the number of vector physical registers. */
165 unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
166 /** @return the number of predicate physical registers. */
167 unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
168
169 /** @return the number of vector physical registers. */
170 unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
171
172 /** @return the number of condition-code physical registers. */
173 unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
174
175 /** @return the total number of physical registers. */
176 unsigned totalNumPhysRegs() const { return totalNumRegs; }
177
178 /** Gets a misc register PhysRegIdPtr. */
179 PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
180 return &miscRegIds[reg_idx];
181 }
182
183 /** Reads an integer register. */
184 RegVal
185 readIntReg(PhysRegIdPtr phys_reg) const
186 {
187 assert(phys_reg->isIntPhysReg());
188
189 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
190 "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
191 return intRegFile[phys_reg->index()];
192 }
193
194 RegVal
195 readFloatReg(PhysRegIdPtr phys_reg) const
196 {
197 assert(phys_reg->isFloatPhysReg());
198
199 RegVal floatRegBits = floatRegFile[phys_reg->index()];
200
201 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
202 "has data %#x\n", phys_reg->index(), floatRegBits);
203
204 return floatRegBits;
205 }
206
207 /** Reads a vector register. */
208 const VecRegContainer &
209 readVecReg(PhysRegIdPtr phys_reg) const
210 {
211 assert(phys_reg->isVectorPhysReg());
212
213 DPRINTF(IEW, "RegFile: Access to vector register %i, has "
214 "data %s\n", int(phys_reg->index()),
215 vectorRegFile[phys_reg->index()].print());
216
217 return vectorRegFile[phys_reg->index()];
218 }
219
220 /** Reads a vector register for modification. */
221 VecRegContainer &
222 getWritableVecReg(PhysRegIdPtr phys_reg)
223 {
224 /* const_cast for not duplicating code above. */
225 return const_cast<VecRegContainer&>(readVecReg(phys_reg));
226 }
227
228 /** Reads a vector register lane. */
229 template <typename VecElem, int LaneIdx>
230 VecLaneT<VecElem, true>
231 readVecLane(PhysRegIdPtr phys_reg) const
232 {
233 return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
234 }
235
236 /** Reads a vector register lane. */
237 template <typename VecElem>
238 VecLaneT<VecElem, true>
239 readVecLane(PhysRegIdPtr phys_reg) const
240 {
241 return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
242 }
243
244 /** Get a vector register lane for modification. */
245 template <typename LD>
246 void
247 setVecLane(PhysRegIdPtr phys_reg, const LD& val)
248 {
249 assert(phys_reg->isVectorPhysReg());
250
251 DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
252 int(phys_reg->index()), phys_reg->elemIndex(), val);
253
254 vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
255 phys_reg->elemIndex()) = val;
256 }
257
258 /** Reads a vector element. */
259 const VecElem &
260 readVecElem(PhysRegIdPtr phys_reg) const
261 {
262 assert(phys_reg->isVectorPhysElem());
263 auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
264 const VecElem& val = ret[phys_reg->elemIndex()];
265 DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
266 " has data %#x\n", phys_reg->elemIndex(),
267 int(phys_reg->index()), val);
268
269 return val;
270 }
271
272 /** Reads a predicate register. */
273 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
274 {
275 assert(phys_reg->isVecPredPhysReg());
276
277 DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
278 "data %s\n", int(phys_reg->index()),
279 vecPredRegFile[phys_reg->index()].print());
280
281 return vecPredRegFile[phys_reg->index()];
282 }
283
284 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
285 {
286 /* const_cast for not duplicating code above. */
287 return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
288 }
289
290 /** Reads a condition-code register. */
291 RegVal
292 readCCReg(PhysRegIdPtr phys_reg)
293 {
294 assert(phys_reg->isCCPhysReg());
295
296 DPRINTF(IEW, "RegFile: Access to cc register %i, has "
297 "data %#x\n", phys_reg->index(),
298 ccRegFile[phys_reg->index()]);
299
300 return ccRegFile[phys_reg->index()];
301 }
302
303 /** Sets an integer register to the given value. */
304 void
305 setIntReg(PhysRegIdPtr phys_reg, RegVal val)
306 {
307 assert(phys_reg->isIntPhysReg());
308
309 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
310 phys_reg->index(), val);
311
312 if (!phys_reg->isZeroReg())
313 intRegFile[phys_reg->index()] = val;
314 }
315
316 void
317 setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
318 {
319 assert(phys_reg->isFloatPhysReg());
320
321 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
322 phys_reg->index(), (uint64_t)val);
323
324 if (!phys_reg->isZeroReg())
325 floatRegFile[phys_reg->index()] = val;
326 }
327
328 /** Sets a vector register to the given value. */
329 void
330 setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
331 {
332 assert(phys_reg->isVectorPhysReg());
333
334 DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
335 int(phys_reg->index()), val.print());
336
337 vectorRegFile[phys_reg->index()] = val;
338 }
339
340 /** Sets a vector register to the given value. */
341 void
342 setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
343 {
344 assert(phys_reg->isVectorPhysElem());
345
346 DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
347 " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
348
349 vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
350 val;
351 }
352
353 /** Sets a predicate register to the given value. */
354 void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
355 {
356 assert(phys_reg->isVecPredPhysReg());
357
358 DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
359 int(phys_reg->index()), val.print());
360
361 vecPredRegFile[phys_reg->index()] = val;
362 }
363
364 /** Sets a condition-code register to the given value. */
365 void
366 setCCReg(PhysRegIdPtr phys_reg, RegVal val)
367 {
368 assert(phys_reg->isCCPhysReg());
369
370 DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
371 phys_reg->index(), (uint64_t)val);
372
373 ccRegFile[phys_reg->index()] = val;
374 }
375
376 /** Get the PhysRegIds of the elems of a vector register.
377 * Auxiliary function to transition from Full vector mode to Elem mode.
378 */
379 IdRange getRegElemIds(PhysRegIdPtr reg);
380
381 /**
382 * Get the PhysRegIds of the elems of all vector registers.
383 * Auxiliary function to transition from Full vector mode to Elem mode
384 * and to initialise the rename map.
385 */
386 IdRange getRegIds(RegClass cls);
387
388 /**
389 * Get the true physical register id.
390 * As many parts work with PhysRegIdPtr, we need to be able to produce
391 * the pointer out of just class and register idx.
392 */
393 PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
394};
395
396
397#endif //__CPU_O3_REGFILE_HH__
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