1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_REGFILE_HH__
30#define __CPU_O3_REGFILE_HH__
31
32#include "arch/isa_traits.hh"
33#include "arch/faults.hh"
34#include "base/trace.hh"
35#include "config/full_system.hh"
36#include "cpu/o3/comm.hh"
37
38#if FULL_SYSTEM
39#include "kern/kernel_stats.hh"
40
41#endif
42
43#include <vector>
44
45/**
46 * Simple physical register file class.
47 * This really only depends on the ISA, and not the Impl. Things that are
48 * in the ifdef FULL_SYSTEM are pretty dependent on the ISA, and probably
49 * should go in the AlphaFullCPU.
50 */
51template <class Impl>
52class PhysRegFile
53{
54 protected:
55 typedef TheISA::IntReg IntReg;
56 typedef TheISA::FloatReg FloatReg;
57 typedef TheISA::MiscRegFile MiscRegFile;
58 typedef TheISA::MiscReg MiscReg;
59 // Note that most of the definitions of the IntReg, FloatReg, etc. exist
60 // within the Impl/ISA class and not within this PhysRegFile class.
61
62 // Will make these registers public for now, but they probably should
63 // be private eventually with some accessor functions.
64 public:
65 typedef typename Impl::FullCPU FullCPU;
66
67 /**
68 * Constructs a physical register file with the specified amount of
69 * integer and floating point registers.
70 */
71 PhysRegFile(unsigned _numPhysicalIntRegs,
72 unsigned _numPhysicalFloatRegs);
73
74 //Everything below should be pretty well identical to the normal
75 //register file that exists within AlphaISA class.
76 //The duplication is unfortunate but it's better than having
77 //different ways to access certain registers.
78
79 //Add these in later when everything else is in place
80// void serialize(std::ostream &os);
81// void unserialize(Checkpoint *cp, const std::string &section);
82
83 /** Reads an integer register. */
84 uint64_t readIntReg(PhysRegIndex reg_idx)
85 {
86 assert(reg_idx < numPhysicalIntRegs);
87
88 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
89 "%i\n", int(reg_idx), intRegFile[reg_idx]);
90 return intRegFile[reg_idx];
91 }

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100 FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
101
102 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
103 "data %8.8d\n", int(reg_idx), (double)floatReg);
104
105 return floatReg;
106 }
107
108 /** Reads a floating point register (double precision). */
109 FloatReg readFloatReg(PhysRegIndex reg_idx)
110 {
111 // Remove the base Float reg dependency.
112 reg_idx = reg_idx - numPhysicalIntRegs;
113
114 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
115
116 FloatReg floatReg = floatRegFile.readReg(reg_idx);
117
118 DPRINTF(IEW, "RegFile: Access to float register %i, has "
119 "data %8.8d\n", int(reg_idx), (double)floatReg);
120
121 return floatReg;
122 }
123
124 /** Reads a floating point register as an integer. */
125 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
126 {
127 // Remove the base Float reg dependency.
128 reg_idx = reg_idx - numPhysicalIntRegs;
129
130 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
131
132 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);

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147 FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
148
149 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
150 "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
151
152 return floatRegBits;
153 }
154
155 /** Sets an integer register to the given value. */
156 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
157 {
158 assert(reg_idx < numPhysicalIntRegs);
159
160 DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
161 int(reg_idx), val);
162
163 if (reg_idx != TheISA::ZeroReg)
164 intRegFile[reg_idx] = val;
165 }
166
167 /** Sets a single precision floating point register to the given value. */
168 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
169 {
170 // Remove the base Float reg dependency.
171 reg_idx = reg_idx - numPhysicalIntRegs;
172
173 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
174
175 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
176 int(reg_idx), (double)val);
177
178 if (reg_idx != TheISA::ZeroReg)
179 floatRegFile.setReg(reg_idx, val, width);
180 }
181
182 /** Sets a double precision floating point register to the given value. */
183 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
184 {
185 // Remove the base Float reg dependency.
186 reg_idx = reg_idx - numPhysicalIntRegs;
187
188 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
189
190 DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
191 int(reg_idx), (double)val);
192
193 if (reg_idx != TheISA::ZeroReg)
194 floatRegFile.setReg(reg_idx, val);
195 }
196
197 /** Sets a floating point register to the given integer value. */
198 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
199 {
200 // Remove the base Float reg dependency.
201 reg_idx = reg_idx - numPhysicalIntRegs;
202
203 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
204
205 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",

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212 {
213 // Remove the base Float reg dependency.
214 reg_idx = reg_idx - numPhysicalIntRegs;
215
216 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
217
218 DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
219 int(reg_idx), (uint64_t)val);
220 }
221
222 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
223 unsigned thread_id)
224 {
225 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
226 cpu->xcBase(thread_id));
227 }
228
229 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
230 {
231 return miscRegs[thread_id].setReg(misc_reg, val);
232 }
233
234 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
235 unsigned thread_id)
236 {
237 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
238 cpu->xcBase(thread_id));
239 }
240
241#if FULL_SYSTEM
242 int readIntrFlag() { return intrflag; }
243 /** Sets an interrupt flag. */
244 void setIntrFlag(int val) { intrflag = val; }
245#endif
246
247 public:
248 /** (signed) integer register file. */
249 std::vector<IntReg> intRegFile;
250
251 /** Floating point register file. */
252 std::vector<FloatReg> floatRegFile;
253
254 /** Miscellaneous register file. */
255 MiscRegFile miscRegs[Impl::MaxThreads];
256
257#if FULL_SYSTEM
258 private:
259 int intrflag; // interrupt flag
260#endif
261
262 private:
263 /** CPU pointer. */
264 FullCPU *cpu;
265
266 public:
267 /** Sets the CPU pointer. */
268 void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; }
269
270 /** Number of physical integer registers. */
271 unsigned numPhysicalIntRegs;
272 /** Number of physical floating point registers. */
273 unsigned numPhysicalFloatRegs;
274};
275
276template <class Impl>
277PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
278 unsigned _numPhysicalFloatRegs)
279 : numPhysicalIntRegs(_numPhysicalIntRegs),
280 numPhysicalFloatRegs(_numPhysicalFloatRegs)
281{
282 intRegFile.resize(numPhysicalIntRegs);
283 floatRegFile.resize(numPhysicalFloatRegs);
284
285 //memset(intRegFile, 0, sizeof(*intRegFile));
286 //memset(floatRegFile, 0, sizeof(*floatRegFile));
287}
288
289#endif