1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/types.hh"
37#include "base/trace.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
40
41#if FULL_SYSTEM
42#include "kern/kernel_stats.hh"
43
44#endif
45
46#include <vector>
47
48/**
49 * Simple physical register file class.
50 * Right now this is specific to Alpha until we decide if/how to make things
51 * generic enough to support other ISAs.
52 */
53template <class Impl>
54class PhysRegFile
55{
56 protected:
57 typedef TheISA::IntReg IntReg;
58 typedef TheISA::FloatReg FloatReg;
59 typedef TheISA::FloatRegBits FloatRegBits;
60 typedef TheISA::MiscRegFile MiscRegFile;
61 typedef TheISA::MiscReg MiscReg;
62
63 typedef union {
64 FloatReg d;
65 FloatRegBits q;
66 } PhysFloatReg;
67
68 // Note that most of the definitions of the IntReg, FloatReg, etc. exist
69 // within the Impl/ISA class and not within this PhysRegFile class.
70
71 // Will make these registers public for now, but they probably should
72 // be private eventually with some accessor functions.
73 public:
74 typedef typename Impl::O3CPU O3CPU;
75
76 /**
77 * Constructs a physical register file with the specified amount of
78 * integer and floating point registers.
79 */
80 PhysRegFile(unsigned _numPhysicalIntRegs,
81 unsigned _numPhysicalFloatRegs);
82
83 //Everything below should be pretty well identical to the normal
84 //register file that exists within AlphaISA class.
85 //The duplication is unfortunate but it's better than having
86 //different ways to access certain registers.
87
88 /** Reads an integer register. */
89 uint64_t readIntReg(PhysRegIndex reg_idx)
90 {
91 assert(reg_idx < numPhysicalIntRegs);
92
93 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
94 "%#x\n", int(reg_idx), intRegFile[reg_idx]);
95 return intRegFile[reg_idx];
96 }
97
98 FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
99 {
100 // Remove the base Float reg dependency.
101 reg_idx = reg_idx - numPhysicalIntRegs;
102
103 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
104
105 FloatReg floatReg = floatRegFile[reg_idx].d;
106
107 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
108 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
109
110 return floatReg;
111 }
112
113 /** Reads a floating point register (double precision). */
114 FloatReg readFloatReg(PhysRegIndex reg_idx)
115 {
116 // Remove the base Float reg dependency.
117 reg_idx = reg_idx - numPhysicalIntRegs;
118
119 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
120
121 FloatReg floatReg = floatRegFile[reg_idx].d;
122
123 DPRINTF(IEW, "RegFile: Access to float register %i, has "
124 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
125
126 return floatReg;
127 }
128
129 /** Reads a floating point register as an integer. */
130 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
131 {
132 // Remove the base Float reg dependency.
133 reg_idx = reg_idx - numPhysicalIntRegs;
134
135 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
136
137 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
138
139 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
140 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
141
142 return floatRegBits;
143 }
144
145 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
146 {
147 // Remove the base Float reg dependency.
148 reg_idx = reg_idx - numPhysicalIntRegs;
149
150 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
151
152 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
153
154 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
155 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
156
157 return floatRegBits;
158 }
159
160 /** Sets an integer register to the given value. */
161 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
162 {
163 assert(reg_idx < numPhysicalIntRegs);
164
165 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
166 int(reg_idx), val);
167
168 if (reg_idx != TheISA::ZeroReg)
169 intRegFile[reg_idx] = val;
170 }
171
172 /** Sets a single precision floating point register to the given value. */
173 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
174 {
175 // Remove the base Float reg dependency.
176 reg_idx = reg_idx - numPhysicalIntRegs;
177
178 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
179
180 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
181 int(reg_idx), (uint64_t)val);
182
183 if (reg_idx != TheISA::ZeroReg)
184 floatRegFile[reg_idx].d = val;
185 }
186
187 /** Sets a double precision floating point register to the given value. */
188 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
189 {
190 // Remove the base Float reg dependency.
191 reg_idx = reg_idx - numPhysicalIntRegs;
192
193 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
194
195 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
196 int(reg_idx), (uint64_t)val);
197
198 if (reg_idx != TheISA::ZeroReg)
199 floatRegFile[reg_idx].d = val;
200 }
201
202 /** Sets a floating point register to the given integer value. */
203 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
204 {
205 // Remove the base Float reg dependency.
206 reg_idx = reg_idx - numPhysicalIntRegs;
207
208 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
209
210 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
211 int(reg_idx), (uint64_t)val);
212
213 floatRegFile[reg_idx].q = val;
214 }
215
216 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
217 {
218 // Remove the base Float reg dependency.
219 reg_idx = reg_idx - numPhysicalIntRegs;
220
221 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
222
223 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
224 int(reg_idx), (uint64_t)val);
225
226 floatRegFile[reg_idx].q = val;
227 }
228
229 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
230 {
231 return miscRegs[thread_id].readReg(misc_reg);
232 }
233
234 MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
235 {
236 return miscRegs[thread_id].readRegWithEffect(misc_reg,
237 cpu->tcBase(thread_id));
238 }
239
240 void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
241 {
242 miscRegs[thread_id].setReg(misc_reg, val);
243 }
244
245 void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
246 unsigned thread_id)
247 {
248 miscRegs[thread_id].setRegWithEffect(misc_reg, val,
249 cpu->tcBase(thread_id));
250 }
251
252 public:
253 /** (signed) integer register file. */
254 IntReg *intRegFile;
255
256 /** Floating point register file. */
257 PhysFloatReg *floatRegFile;
258
259 /** Miscellaneous register file. */
260 MiscRegFile miscRegs[Impl::MaxThreads];
261
262#if FULL_SYSTEM
263 private:
264 int intrflag; // interrupt flag
265#endif
266
267 private:
268 /** CPU pointer. */
269 O3CPU *cpu;
270
271 public:
272 /** Sets the CPU pointer. */
273 void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
274
275 /** Number of physical integer registers. */
276 unsigned numPhysicalIntRegs;
277 /** Number of physical floating point registers. */
278 unsigned numPhysicalFloatRegs;
279};
280
281template <class Impl>
282PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
283 unsigned _numPhysicalFloatRegs)
284 : numPhysicalIntRegs(_numPhysicalIntRegs),
285 numPhysicalFloatRegs(_numPhysicalFloatRegs)
286{
287 intRegFile = new IntReg[numPhysicalIntRegs];
288 floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
289
290 for (int i = 0; i < Impl::MaxThreads; ++i) {
291 miscRegs[i].clear();
292 }
293
294 memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
295 memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
296}
297
298#endif
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/types.hh"
37#include "base/trace.hh"
38#include "config/full_system.hh"
39#include "cpu/o3/comm.hh"
40
41#if FULL_SYSTEM
42#include "kern/kernel_stats.hh"
43
44#endif
45
46#include <vector>
47
48/**
49 * Simple physical register file class.
50 * Right now this is specific to Alpha until we decide if/how to make things
51 * generic enough to support other ISAs.
52 */
53template <class Impl>
54class PhysRegFile
55{
56 protected:
57 typedef TheISA::IntReg IntReg;
58 typedef TheISA::FloatReg FloatReg;
59 typedef TheISA::FloatRegBits FloatRegBits;
60 typedef TheISA::MiscRegFile MiscRegFile;
61 typedef TheISA::MiscReg MiscReg;
62
63 typedef union {
64 FloatReg d;
65 FloatRegBits q;
66 } PhysFloatReg;
67
68 // Note that most of the definitions of the IntReg, FloatReg, etc. exist
69 // within the Impl/ISA class and not within this PhysRegFile class.
70
71 // Will make these registers public for now, but they probably should
72 // be private eventually with some accessor functions.
73 public:
74 typedef typename Impl::O3CPU O3CPU;
75
76 /**
77 * Constructs a physical register file with the specified amount of
78 * integer and floating point registers.
79 */
80 PhysRegFile(unsigned _numPhysicalIntRegs,
81 unsigned _numPhysicalFloatRegs);
82
83 //Everything below should be pretty well identical to the normal
84 //register file that exists within AlphaISA class.
85 //The duplication is unfortunate but it's better than having
86 //different ways to access certain registers.
87
88 /** Reads an integer register. */
89 uint64_t readIntReg(PhysRegIndex reg_idx)
90 {
91 assert(reg_idx < numPhysicalIntRegs);
92
93 DPRINTF(IEW, "RegFile: Access to int register %i, has data "
94 "%#x\n", int(reg_idx), intRegFile[reg_idx]);
95 return intRegFile[reg_idx];
96 }
97
98 FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
99 {
100 // Remove the base Float reg dependency.
101 reg_idx = reg_idx - numPhysicalIntRegs;
102
103 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
104
105 FloatReg floatReg = floatRegFile[reg_idx].d;
106
107 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
108 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
109
110 return floatReg;
111 }
112
113 /** Reads a floating point register (double precision). */
114 FloatReg readFloatReg(PhysRegIndex reg_idx)
115 {
116 // Remove the base Float reg dependency.
117 reg_idx = reg_idx - numPhysicalIntRegs;
118
119 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
120
121 FloatReg floatReg = floatRegFile[reg_idx].d;
122
123 DPRINTF(IEW, "RegFile: Access to float register %i, has "
124 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
125
126 return floatReg;
127 }
128
129 /** Reads a floating point register as an integer. */
130 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
131 {
132 // Remove the base Float reg dependency.
133 reg_idx = reg_idx - numPhysicalIntRegs;
134
135 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
136
137 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
138
139 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
140 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
141
142 return floatRegBits;
143 }
144
145 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
146 {
147 // Remove the base Float reg dependency.
148 reg_idx = reg_idx - numPhysicalIntRegs;
149
150 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
151
152 FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
153
154 DPRINTF(IEW, "RegFile: Access to float register %i as int, "
155 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
156
157 return floatRegBits;
158 }
159
160 /** Sets an integer register to the given value. */
161 void setIntReg(PhysRegIndex reg_idx, uint64_t val)
162 {
163 assert(reg_idx < numPhysicalIntRegs);
164
165 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
166 int(reg_idx), val);
167
168 if (reg_idx != TheISA::ZeroReg)
169 intRegFile[reg_idx] = val;
170 }
171
172 /** Sets a single precision floating point register to the given value. */
173 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
174 {
175 // Remove the base Float reg dependency.
176 reg_idx = reg_idx - numPhysicalIntRegs;
177
178 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
179
180 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
181 int(reg_idx), (uint64_t)val);
182
183 if (reg_idx != TheISA::ZeroReg)
184 floatRegFile[reg_idx].d = val;
185 }
186
187 /** Sets a double precision floating point register to the given value. */
188 void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
189 {
190 // Remove the base Float reg dependency.
191 reg_idx = reg_idx - numPhysicalIntRegs;
192
193 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
194
195 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
196 int(reg_idx), (uint64_t)val);
197
198 if (reg_idx != TheISA::ZeroReg)
199 floatRegFile[reg_idx].d = val;
200 }
201
202 /** Sets a floating point register to the given integer value. */
203 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
204 {
205 // Remove the base Float reg dependency.
206 reg_idx = reg_idx - numPhysicalIntRegs;
207
208 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
209
210 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
211 int(reg_idx), (uint64_t)val);
212
213 floatRegFile[reg_idx].q = val;
214 }
215
216 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
217 {
218 // Remove the base Float reg dependency.
219 reg_idx = reg_idx - numPhysicalIntRegs;
220
221 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
222
223 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
224 int(reg_idx), (uint64_t)val);
225
226 floatRegFile[reg_idx].q = val;
227 }
228
229 MiscReg readMiscReg(int misc_reg, unsigned thread_id)
230 {
231 return miscRegs[thread_id].readReg(misc_reg);
232 }
233
234 MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
235 {
236 return miscRegs[thread_id].readRegWithEffect(misc_reg,
237 cpu->tcBase(thread_id));
238 }
239
240 void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
241 {
242 miscRegs[thread_id].setReg(misc_reg, val);
243 }
244
245 void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
246 unsigned thread_id)
247 {
248 miscRegs[thread_id].setRegWithEffect(misc_reg, val,
249 cpu->tcBase(thread_id));
250 }
251
252 public:
253 /** (signed) integer register file. */
254 IntReg *intRegFile;
255
256 /** Floating point register file. */
257 PhysFloatReg *floatRegFile;
258
259 /** Miscellaneous register file. */
260 MiscRegFile miscRegs[Impl::MaxThreads];
261
262#if FULL_SYSTEM
263 private:
264 int intrflag; // interrupt flag
265#endif
266
267 private:
268 /** CPU pointer. */
269 O3CPU *cpu;
270
271 public:
272 /** Sets the CPU pointer. */
273 void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; }
274
275 /** Number of physical integer registers. */
276 unsigned numPhysicalIntRegs;
277 /** Number of physical floating point registers. */
278 unsigned numPhysicalFloatRegs;
279};
280
281template <class Impl>
282PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
283 unsigned _numPhysicalFloatRegs)
284 : numPhysicalIntRegs(_numPhysicalIntRegs),
285 numPhysicalFloatRegs(_numPhysicalFloatRegs)
286{
287 intRegFile = new IntReg[numPhysicalIntRegs];
288 floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
289
290 for (int i = 0; i < Impl::MaxThreads; ++i) {
291 miscRegs[i].clear();
292 }
293
294 memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
295 memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
296}
297
298#endif