1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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246
247 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
248 unsigned thread_id)
249 {
250 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
251 cpu->tcBase(thread_id));
252 }
253
254 public:
255 /** (signed) integer register file. */
256 IntReg *intRegFile;
257
258 /** Floating point register file. */
259 PhysFloatReg *floatRegFile;
260
261 /** Miscellaneous register file. */
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2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 237 unchanged lines hidden (view full) ---
246
247 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
248 unsigned thread_id)
249 {
250 return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
251 cpu->tcBase(thread_id));
252 }
253
254 public:
255 /** (signed) integer register file. */
256 IntReg *intRegFile;
257
258 /** Floating point register file. */
259 PhysFloatReg *floatRegFile;
260
261 /** Miscellaneous register file. */
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