regfile.cc (12109:f29e9c5418aa) regfile.cc (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2016 ARM Limited
2 * Copyright (c) 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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47
48#include "cpu/o3/free_list.hh"
49#include "arch/generic/types.hh"
50#include "cpu/o3/free_list.hh"
51
52PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
53 unsigned _numPhysicalFloatRegs,
54 unsigned _numPhysicalVecRegs,
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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47
48#include "cpu/o3/free_list.hh"
49#include "arch/generic/types.hh"
50#include "cpu/o3/free_list.hh"
51
52PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
53 unsigned _numPhysicalFloatRegs,
54 unsigned _numPhysicalVecRegs,
55 unsigned _numPhysicalVecPredRegs,
55 unsigned _numPhysicalCCRegs,
56 VecMode vmode)
57 : intRegFile(_numPhysicalIntRegs),
58 floatRegFile(_numPhysicalFloatRegs),
59 vectorRegFile(_numPhysicalVecRegs),
56 unsigned _numPhysicalCCRegs,
57 VecMode vmode)
58 : intRegFile(_numPhysicalIntRegs),
59 floatRegFile(_numPhysicalFloatRegs),
60 vectorRegFile(_numPhysicalVecRegs),
61 vecPredRegFile(_numPhysicalVecPredRegs),
60 ccRegFile(_numPhysicalCCRegs),
61 numPhysicalIntRegs(_numPhysicalIntRegs),
62 numPhysicalFloatRegs(_numPhysicalFloatRegs),
63 numPhysicalVecRegs(_numPhysicalVecRegs),
64 numPhysicalVecElemRegs(_numPhysicalVecRegs *
65 NumVecElemPerVecReg),
62 ccRegFile(_numPhysicalCCRegs),
63 numPhysicalIntRegs(_numPhysicalIntRegs),
64 numPhysicalFloatRegs(_numPhysicalFloatRegs),
65 numPhysicalVecRegs(_numPhysicalVecRegs),
66 numPhysicalVecElemRegs(_numPhysicalVecRegs *
67 NumVecElemPerVecReg),
68 numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
66 numPhysicalCCRegs(_numPhysicalCCRegs),
67 totalNumRegs(_numPhysicalIntRegs
68 + _numPhysicalFloatRegs
69 + _numPhysicalVecRegs
70 + _numPhysicalVecRegs * NumVecElemPerVecReg
69 numPhysicalCCRegs(_numPhysicalCCRegs),
70 totalNumRegs(_numPhysicalIntRegs
71 + _numPhysicalFloatRegs
72 + _numPhysicalVecRegs
73 + _numPhysicalVecRegs * NumVecElemPerVecReg
74 + _numPhysicalVecPredRegs
71 + _numPhysicalCCRegs),
72 vecMode(vmode)
73{
74 PhysRegIndex phys_reg;
75 PhysRegIndex flat_reg_idx = 0;
76
77 if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
78 // Just make this a warning and go ahead and allocate them

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103 // them; put them onto the vector free list.
104 for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
105 for (ElemIndex eIdx = 0; eIdx < NumVecElemPerVecReg; eIdx++) {
106 vecElemIds.emplace_back(VecElemClass, phys_reg,
107 eIdx, flat_reg_idx++);
108 }
109 }
110
75 + _numPhysicalCCRegs),
76 vecMode(vmode)
77{
78 PhysRegIndex phys_reg;
79 PhysRegIndex flat_reg_idx = 0;
80
81 if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
82 // Just make this a warning and go ahead and allocate them

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107 // them; put them onto the vector free list.
108 for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
109 for (ElemIndex eIdx = 0; eIdx < NumVecElemPerVecReg; eIdx++) {
110 vecElemIds.emplace_back(VecElemClass, phys_reg,
111 eIdx, flat_reg_idx++);
112 }
113 }
114
115 // The next batch of the registers are the predicate physical
116 // registers; put them onto the predicate free list.
117 for (phys_reg = 0; phys_reg < numPhysicalVecPredRegs; phys_reg++) {
118 vecPredRegIds.emplace_back(VecPredRegClass, phys_reg, flat_reg_idx++);
119 }
120
111 // The rest of the registers are the condition-code physical
112 // registers; put them onto the condition-code free list.
113 for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
114 ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
115 }
116
117 // Misc regs have a fixed mapping but still need PhysRegIds.
118 for (phys_reg = 0; phys_reg < TheISA::NumMiscRegs; phys_reg++) {

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154
155 /* depending on the mode we add the vector registers as whole units or
156 * as different elements. */
157 if (vecMode == Enums::Full)
158 freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
159 else
160 freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
161
121 // The rest of the registers are the condition-code physical
122 // registers; put them onto the condition-code free list.
123 for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
124 ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
125 }
126
127 // Misc regs have a fixed mapping but still need PhysRegIds.
128 for (phys_reg = 0; phys_reg < TheISA::NumMiscRegs; phys_reg++) {

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164
165 /* depending on the mode we add the vector registers as whole units or
166 * as different elements. */
167 if (vecMode == Enums::Full)
168 freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
169 else
170 freeList->addRegs(vecElemIds.begin(), vecElemIds.end());
171
172 // The next batch of the registers are the predicate physical
173 // registers; put them onto the predicate free list.
174 for (reg_idx = 0; reg_idx < numPhysicalVecPredRegs; reg_idx++) {
175 assert(vecPredRegIds[reg_idx].index() == reg_idx);
176 }
177 freeList->addRegs(vecPredRegIds.begin(), vecPredRegIds.end());
178
162 // The rest of the registers are the condition-code physical
163 // registers; put them onto the condition-code free list.
164 for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
165 assert(ccRegIds[reg_idx].index() == reg_idx);
166 }
167 freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
168}
169

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186 case IntRegClass:
187 return std::make_pair(intRegIds.begin(), intRegIds.end());
188 case FloatRegClass:
189 return std::make_pair(floatRegIds.begin(), floatRegIds.end());
190 case VecRegClass:
191 return std::make_pair(vecRegIds.begin(), vecRegIds.end());
192 case VecElemClass:
193 return std::make_pair(vecElemIds.begin(), vecElemIds.end());
179 // The rest of the registers are the condition-code physical
180 // registers; put them onto the condition-code free list.
181 for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
182 assert(ccRegIds[reg_idx].index() == reg_idx);
183 }
184 freeList->addRegs(ccRegIds.begin(), ccRegIds.end());
185}
186

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203 case IntRegClass:
204 return std::make_pair(intRegIds.begin(), intRegIds.end());
205 case FloatRegClass:
206 return std::make_pair(floatRegIds.begin(), floatRegIds.end());
207 case VecRegClass:
208 return std::make_pair(vecRegIds.begin(), vecRegIds.end());
209 case VecElemClass:
210 return std::make_pair(vecElemIds.begin(), vecElemIds.end());
211 case VecPredRegClass:
212 return std::make_pair(vecPredRegIds.begin(), vecPredRegIds.end());
194 case CCRegClass:
195 return std::make_pair(ccRegIds.begin(), ccRegIds.end());
196 case MiscRegClass:
197 return std::make_pair(miscRegIds.begin(), miscRegIds.end());
198 }
199 /* There is no way to make an empty iterator */
200 return std::make_pair(PhysIds::const_iterator(),
201 PhysIds::const_iterator());

--- 18 unchanged lines hidden --- 		213 case CCRegClass:
214 return std::make_pair(ccRegIds.begin(), ccRegIds.end());
215 case MiscRegClass:
216 return std::make_pair(miscRegIds.begin(), miscRegIds.end());
217 }
218 /* There is no way to make an empty iterator */
219 return std::make_pair(PhysIds::const_iterator(),
220 PhysIds::const_iterator());

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