44,45c44,46
< baseFloatRegIndex(_numPhysicalIntRegs),
< baseCCRegIndex(_numPhysicalIntRegs + _numPhysicalFloatRegs),
---
> numPhysicalIntRegs(_numPhysicalIntRegs),
> numPhysicalFloatRegs(_numPhysicalFloatRegs),
> numPhysicalCCRegs(_numPhysicalCCRegs),
49a51,53
> PhysRegIndex phys_reg;
> PhysRegIndex flat_reg_idx = 0;
>
55a60,80
> // The initial batch of registers are the integer ones
> for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
> intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
> }
>
> // The next batch of the registers are the floating-point physical
> // registers; put them onto the floating-point free list.
> for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
> floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
> }
>
> // The rest of the registers are the condition-code physical
> // registers; put them onto the condition-code free list.
> for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
> ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
> }
>
> // Misc regs have a fixed mapping but still need PhysRegIds.
> for (phys_reg = 0; phys_reg < TheISA::NumMiscRegs; phys_reg++) {
> miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
> }
63c88
< PhysRegIndex reg_idx = 0;
---
> int reg_idx = 0;
66,67c91,93
< while (reg_idx < baseFloatRegIndex) {
< freeList->addIntReg(reg_idx++);
---
> for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) {
> assert(intRegIds[reg_idx].regIdx == reg_idx);
> freeList->addIntReg(&intRegIds[reg_idx]);
72,73c98,100
< while (reg_idx < baseCCRegIndex) {
< freeList->addFloatReg(reg_idx++);
---
> for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) {
> assert(floatRegIds[reg_idx].regIdx == reg_idx);
> freeList->addFloatReg(&floatRegIds[reg_idx]);
78,79c105,107
< while (reg_idx < totalNumRegs) {
< freeList->addCCReg(reg_idx++);
---
> for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
> assert(ccRegIds[reg_idx].regIdx == reg_idx);
> freeList->addCCReg(&ccRegIds[reg_idx]);