1/* 2 * Copyright (c) 2013 - 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 78 unchanged lines hidden (view full) --- 87 */ 88class ElasticTrace : public ProbeListenerObject 89{ 90 91 public: 92 typedef typename O3CPUImpl::DynInstPtr DynInstPtr; 93 typedef typename std::pair<InstSeqNum, PhysRegIndex> SeqNumRegPair; 94 |
95 /** Trace record types corresponding to instruction node types */ 96 typedef ProtoMessage::InstDepRecord::RecordType RecordType; 97 typedef ProtoMessage::InstDepRecord Record; 98 |
99 /** Constructor */ 100 ElasticTrace(const ElasticTraceParams *params); 101 102 /** 103 * Register the probe listeners that is the methods called on a probe point 104 * notify() call. 105 */ 106 void regProbeListeners(); --- 152 unchanged lines hidden (view full) --- 259 struct TraceInfo 260 { 261 /** 262 * @ingroup TraceInfo 263 * @{ 264 */ 265 /* Instruction sequence number. */ 266 InstSeqNum instNum; |
267 /** The type of trace record for the instruction node */ 268 RecordType type; |
269 /* Tick when instruction was in execute stage. */ 270 Tick executeTick; 271 /* Tick when instruction was marked ready and sent to commit stage. */ 272 Tick toCommitTick; 273 /* Tick when instruction was committed. */ 274 Tick commitTick; |
275 /* If instruction was committed, as against squashed. */ 276 bool commit; |
277 /* List of order dependencies. */ 278 std::list<InstSeqNum> robDepList; 279 /* List of physical register RAW dependencies. */ 280 std::list<InstSeqNum> physRegDepList; 281 /** 282 * Computational delay after the last dependent inst. completed. 283 * A value of -1 which means instruction has no dependencies. 284 */ 285 int64_t compDelay; 286 /* Number of dependents. */ 287 uint32_t numDepts; 288 /* The instruction PC for a load, store or non load/store. */ 289 Addr pc; 290 /* Request flags in case of a load/store instruction */ 291 Request::FlagsType reqFlags; 292 /* Request address in case of a load/store instruction */ 293 Addr addr; 294 /* Request size in case of a load/store instruction */ 295 unsigned size; |
296 /** Default Constructor */ 297 TraceInfo() 298 : type(Record::INVALID) 299 { } 300 /** Is the record a load */ 301 bool isLoad() const { return (type == Record::LOAD); } 302 /** Is the record a store */ 303 bool isStore() const { return (type == Record::STORE); } 304 /** Is the record a fetch triggering an Icache request */ 305 bool isComp() const { return (type == Record::COMP); } 306 /** Return string specifying the type of the node */ 307 const std::string& typeToStr() const; |
308 /** @} */ 309 310 /** 311 * Get the execute tick of the instruction. 312 * 313 * @return Tick when instruction was executed 314 */ 315 Tick getExecuteTick() const; --- 240 unchanged lines hidden --- |