1/*
2 * Copyright (c) 2013 - 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Radhika Jagtap
38 * Andreas Hansson
39 * Thomas Grass
40 */
41
42/**
43 * @file This file describes a trace component which is a cpu probe listener
44 * used to generate elastic cpu traces. It registers listeners to probe points
45 * in the fetch, rename, iew and commit stages of the O3CPU. It processes the
46 * dependency graph of the cpu execution and writes out a protobuf trace. It
47 * also generates a protobuf trace of the instruction fetch requests.
48 */
49
50#ifndef __CPU_O3_PROBE_ELASTIC_TRACE_HH__
51#define __CPU_O3_PROBE_ELASTIC_TRACE_HH__
52
53#include <set>
54#include <unordered_map>
55#include <utility>
56
57#include "cpu/o3/dyn_inst.hh"
58#include "cpu/o3/impl.hh"
59#include "mem/request.hh"
60#include "params/ElasticTrace.hh"
61#include "proto/inst_dep_record.pb.h"
62#include "proto/packet.pb.h"
63#include "proto/protoio.hh"
64#include "sim/eventq.hh"
65#include "sim/probe/probe.hh"
66
67/**
68 * The elastic trace is a type of probe listener and listens to probe points
69 * in multiple stages of the O3CPU. The notify method is called on a probe
70 * point typically when an instruction successfully progresses through that
71 * stage.
72 *
73 * As different listener methods mapped to the different probe points execute,
74 * relevant information about the instruction, e.g. timestamps and register
75 * accesses, are captured and stored in temporary data structures. When the
76 * instruction progresses through the commit stage, the timing as well as
77 * dependency information about the instruction is finalised and encapsulated in
78 * a struct called TraceInfo. TraceInfo objects are collected in a list instead
79 * of writing them out to the trace file one a time. This is required as the
80 * trace is processed in chunks to evaluate order dependencies and computational
81 * delay in case an instruction does not have any register dependencies. By this
82 * we achieve a simpler algorithm during replay because every record in the
83 * trace can be hooked onto a record in its past. The trace is written out as
84 * a protobuf format output file.
85 *
86 * The output trace can be read in and played back by the TraceCPU.
87 */
88class ElasticTrace : public ProbeListenerObject
89{
90
91 public:
92 typedef typename O3CPUImpl::DynInstPtr DynInstPtr;
93 typedef typename std::pair<InstSeqNum, PhysRegIndex> SeqNumRegPair;
94
| 1/*
2 * Copyright (c) 2013 - 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Radhika Jagtap
38 * Andreas Hansson
39 * Thomas Grass
40 */
41
42/**
43 * @file This file describes a trace component which is a cpu probe listener
44 * used to generate elastic cpu traces. It registers listeners to probe points
45 * in the fetch, rename, iew and commit stages of the O3CPU. It processes the
46 * dependency graph of the cpu execution and writes out a protobuf trace. It
47 * also generates a protobuf trace of the instruction fetch requests.
48 */
49
50#ifndef __CPU_O3_PROBE_ELASTIC_TRACE_HH__
51#define __CPU_O3_PROBE_ELASTIC_TRACE_HH__
52
53#include <set>
54#include <unordered_map>
55#include <utility>
56
57#include "cpu/o3/dyn_inst.hh"
58#include "cpu/o3/impl.hh"
59#include "mem/request.hh"
60#include "params/ElasticTrace.hh"
61#include "proto/inst_dep_record.pb.h"
62#include "proto/packet.pb.h"
63#include "proto/protoio.hh"
64#include "sim/eventq.hh"
65#include "sim/probe/probe.hh"
66
67/**
68 * The elastic trace is a type of probe listener and listens to probe points
69 * in multiple stages of the O3CPU. The notify method is called on a probe
70 * point typically when an instruction successfully progresses through that
71 * stage.
72 *
73 * As different listener methods mapped to the different probe points execute,
74 * relevant information about the instruction, e.g. timestamps and register
75 * accesses, are captured and stored in temporary data structures. When the
76 * instruction progresses through the commit stage, the timing as well as
77 * dependency information about the instruction is finalised and encapsulated in
78 * a struct called TraceInfo. TraceInfo objects are collected in a list instead
79 * of writing them out to the trace file one a time. This is required as the
80 * trace is processed in chunks to evaluate order dependencies and computational
81 * delay in case an instruction does not have any register dependencies. By this
82 * we achieve a simpler algorithm during replay because every record in the
83 * trace can be hooked onto a record in its past. The trace is written out as
84 * a protobuf format output file.
85 *
86 * The output trace can be read in and played back by the TraceCPU.
87 */
88class ElasticTrace : public ProbeListenerObject
89{
90
91 public:
92 typedef typename O3CPUImpl::DynInstPtr DynInstPtr;
93 typedef typename std::pair<InstSeqNum, PhysRegIndex> SeqNumRegPair;
94
|
| 95 /** Trace record types corresponding to instruction node types */
96 typedef ProtoMessage::InstDepRecord::RecordType RecordType;
97 typedef ProtoMessage::InstDepRecord Record;
98
|
95 /** Constructor */
96 ElasticTrace(const ElasticTraceParams *params);
97
98 /**
99 * Register the probe listeners that is the methods called on a probe point
100 * notify() call.
101 */
102 void regProbeListeners();
103
104 /** Register all listeners. */
105 void regEtraceListeners();
106
107 /** Returns the name of the trace probe listener. */
108 const std::string name() const;
109
110 /**
111 * Process any outstanding trace records, flush them out to the protobuf
112 * output streams and delete the streams at simulation exit.
113 */
114 void flushTraces();
115
116 /**
117 * Take the fields of the request class object that are relevant to create
118 * an instruction fetch request. It creates a protobuf message containing
119 * the request fields and writes it to instTraceStream.
120 *
121 * @param req pointer to the fetch request
122 */
123 void fetchReqTrace(const RequestPtr &req);
124
125 /**
126 * Populate the execute timestamp field in an InstExecInfo object for an
127 * instruction in flight.
128 *
129 * @param dyn_inst pointer to dynamic instruction in flight
130 */
131 void recordExecTick(const DynInstPtr &dyn_inst);
132
133 /**
134 * Populate the timestamp field in an InstExecInfo object for an
135 * instruction in flight when it is execution is complete and it is ready
136 * to commit.
137 *
138 * @param dyn_inst pointer to dynamic instruction in flight
139 */
140 void recordToCommTick(const DynInstPtr &dyn_inst);
141
142 /**
143 * Record a Read After Write physical register dependency if there has
144 * been a write to the source register and update the physical register
145 * map. For this look up the physRegDepMap with this instruction as the
146 * writer of its destination register. If the dependency falls outside the
147 * window it is assumed as already complete. Duplicate entries are avoided.
148 *
149 * @param dyn_inst pointer to dynamic instruction in flight
150 */
151 void updateRegDep(const DynInstPtr &dyn_inst);
152
153 /**
154 * When an instruction gets squashed the destination register mapped to it
155 * is freed up in the rename stage. Remove the register entry from the
156 * physRegDepMap as well to avoid dependencies on squashed instructions.
157 *
158 * @param inst_reg_pair pair of inst. sequence no. and the register
159 */
160 void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair);
161
162 /**
163 * Add an instruction that is at the head of the ROB and is squashed only
164 * if it is a load and a request was sent for it.
165 *
166 * @param head_inst pointer to dynamic instruction to be squashed
167 */
168 void addSquashedInst(const DynInstPtr &head_inst);
169
170 /**
171 * Add an instruction that is at the head of the ROB and is committed.
172 *
173 * @param head_inst pointer to dynamic instruction to be committed
174 */
175 void addCommittedInst(const DynInstPtr &head_inst);
176
177 /** Register statistics for the elastic trace. */
178 void regStats();
179
180 /** Event to trigger registering this listener for all probe points. */
181 EventWrapper<ElasticTrace,
182 &ElasticTrace::regEtraceListeners> regEtraceListenersEvent;
183
184 private:
185 /**
186 * Used for checking the first window for processing and writing of
187 * dependency trace. At the start of the program there can be dependency-
188 * free instructions and such cases are handled differently.
189 */
190 bool firstWin;
191
192 /**
193 * @defgroup InstExecInfo Struct for storing information before an
194 * instruction reaches the commit stage, e.g. execute timestamp.
195 */
196 struct InstExecInfo
197 {
198 /**
199 * @ingroup InstExecInfo
200 * @{
201 */
202 /** Timestamp when instruction was first processed by execute stage */
203 Tick executeTick;
204 /**
205 * Timestamp when instruction execution is completed in execute stage
206 * and instruction is marked as ready to commit
207 */
208 Tick toCommitTick;
209 /**
210 * Set of instruction sequence numbers that this instruction depends on
211 * due to Read After Write data dependency based on physical register.
212 */
213 std::set<InstSeqNum> physRegDepSet;
214 /** @} */
215
216 /** Constructor */
217 InstExecInfo()
218 : executeTick(MaxTick),
219 toCommitTick(MaxTick)
220 { }
221 };
222
223 /**
224 * Temporary store of InstExecInfo objects. Later on when an instruction
225 * is processed for commit or retire, if it is chosen to be written to
226 * the output trace then this information is looked up using the instruction
227 * sequence number as the key. If it is not chosen then the entry for it in
228 * the store is cleared.
229 */
230 std::unordered_map<InstSeqNum, InstExecInfo*> tempStore;
231
232 /**
233 * The last cleared instruction sequence number used to free up the memory
234 * allocated in the temporary store.
235 */
236 InstSeqNum lastClearedSeqNum;
237
238 /**
239 * Map for recording the producer of a physical register to check Read
240 * After Write dependencies. The key is the renamed physical register and
241 * the value is the instruction sequence number of its last producer.
242 */
243 std::unordered_map<PhysRegIndex, InstSeqNum> physRegDepMap;
244
245 /**
246 * @defgroup TraceInfo Struct for a record in the instruction dependency
247 * trace. All information required to process and calculate the
248 * computational delay is stored in TraceInfo objects. The memory request
249 * fields for a load or store instruction are also included here. Note
250 * that the structure TraceInfo does not store pointers to children
251 * or parents. The dependency trace is maintained as an ordered collection
252 * of records for writing to the output trace and not as a tree data
253 * structure.
254 */
255 struct TraceInfo
256 {
257 /**
258 * @ingroup TraceInfo
259 * @{
260 */
261 /* Instruction sequence number. */
262 InstSeqNum instNum;
| 99 /** Constructor */
100 ElasticTrace(const ElasticTraceParams *params);
101
102 /**
103 * Register the probe listeners that is the methods called on a probe point
104 * notify() call.
105 */
106 void regProbeListeners();
107
108 /** Register all listeners. */
109 void regEtraceListeners();
110
111 /** Returns the name of the trace probe listener. */
112 const std::string name() const;
113
114 /**
115 * Process any outstanding trace records, flush them out to the protobuf
116 * output streams and delete the streams at simulation exit.
117 */
118 void flushTraces();
119
120 /**
121 * Take the fields of the request class object that are relevant to create
122 * an instruction fetch request. It creates a protobuf message containing
123 * the request fields and writes it to instTraceStream.
124 *
125 * @param req pointer to the fetch request
126 */
127 void fetchReqTrace(const RequestPtr &req);
128
129 /**
130 * Populate the execute timestamp field in an InstExecInfo object for an
131 * instruction in flight.
132 *
133 * @param dyn_inst pointer to dynamic instruction in flight
134 */
135 void recordExecTick(const DynInstPtr &dyn_inst);
136
137 /**
138 * Populate the timestamp field in an InstExecInfo object for an
139 * instruction in flight when it is execution is complete and it is ready
140 * to commit.
141 *
142 * @param dyn_inst pointer to dynamic instruction in flight
143 */
144 void recordToCommTick(const DynInstPtr &dyn_inst);
145
146 /**
147 * Record a Read After Write physical register dependency if there has
148 * been a write to the source register and update the physical register
149 * map. For this look up the physRegDepMap with this instruction as the
150 * writer of its destination register. If the dependency falls outside the
151 * window it is assumed as already complete. Duplicate entries are avoided.
152 *
153 * @param dyn_inst pointer to dynamic instruction in flight
154 */
155 void updateRegDep(const DynInstPtr &dyn_inst);
156
157 /**
158 * When an instruction gets squashed the destination register mapped to it
159 * is freed up in the rename stage. Remove the register entry from the
160 * physRegDepMap as well to avoid dependencies on squashed instructions.
161 *
162 * @param inst_reg_pair pair of inst. sequence no. and the register
163 */
164 void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair);
165
166 /**
167 * Add an instruction that is at the head of the ROB and is squashed only
168 * if it is a load and a request was sent for it.
169 *
170 * @param head_inst pointer to dynamic instruction to be squashed
171 */
172 void addSquashedInst(const DynInstPtr &head_inst);
173
174 /**
175 * Add an instruction that is at the head of the ROB and is committed.
176 *
177 * @param head_inst pointer to dynamic instruction to be committed
178 */
179 void addCommittedInst(const DynInstPtr &head_inst);
180
181 /** Register statistics for the elastic trace. */
182 void regStats();
183
184 /** Event to trigger registering this listener for all probe points. */
185 EventWrapper<ElasticTrace,
186 &ElasticTrace::regEtraceListeners> regEtraceListenersEvent;
187
188 private:
189 /**
190 * Used for checking the first window for processing and writing of
191 * dependency trace. At the start of the program there can be dependency-
192 * free instructions and such cases are handled differently.
193 */
194 bool firstWin;
195
196 /**
197 * @defgroup InstExecInfo Struct for storing information before an
198 * instruction reaches the commit stage, e.g. execute timestamp.
199 */
200 struct InstExecInfo
201 {
202 /**
203 * @ingroup InstExecInfo
204 * @{
205 */
206 /** Timestamp when instruction was first processed by execute stage */
207 Tick executeTick;
208 /**
209 * Timestamp when instruction execution is completed in execute stage
210 * and instruction is marked as ready to commit
211 */
212 Tick toCommitTick;
213 /**
214 * Set of instruction sequence numbers that this instruction depends on
215 * due to Read After Write data dependency based on physical register.
216 */
217 std::set<InstSeqNum> physRegDepSet;
218 /** @} */
219
220 /** Constructor */
221 InstExecInfo()
222 : executeTick(MaxTick),
223 toCommitTick(MaxTick)
224 { }
225 };
226
227 /**
228 * Temporary store of InstExecInfo objects. Later on when an instruction
229 * is processed for commit or retire, if it is chosen to be written to
230 * the output trace then this information is looked up using the instruction
231 * sequence number as the key. If it is not chosen then the entry for it in
232 * the store is cleared.
233 */
234 std::unordered_map<InstSeqNum, InstExecInfo*> tempStore;
235
236 /**
237 * The last cleared instruction sequence number used to free up the memory
238 * allocated in the temporary store.
239 */
240 InstSeqNum lastClearedSeqNum;
241
242 /**
243 * Map for recording the producer of a physical register to check Read
244 * After Write dependencies. The key is the renamed physical register and
245 * the value is the instruction sequence number of its last producer.
246 */
247 std::unordered_map<PhysRegIndex, InstSeqNum> physRegDepMap;
248
249 /**
250 * @defgroup TraceInfo Struct for a record in the instruction dependency
251 * trace. All information required to process and calculate the
252 * computational delay is stored in TraceInfo objects. The memory request
253 * fields for a load or store instruction are also included here. Note
254 * that the structure TraceInfo does not store pointers to children
255 * or parents. The dependency trace is maintained as an ordered collection
256 * of records for writing to the output trace and not as a tree data
257 * structure.
258 */
259 struct TraceInfo
260 {
261 /**
262 * @ingroup TraceInfo
263 * @{
264 */
265 /* Instruction sequence number. */
266 InstSeqNum instNum;
|
| 267 /** The type of trace record for the instruction node */
268 RecordType type;
|
263 /* Tick when instruction was in execute stage. */
264 Tick executeTick;
265 /* Tick when instruction was marked ready and sent to commit stage. */
266 Tick toCommitTick;
267 /* Tick when instruction was committed. */
268 Tick commitTick;
| 269 /* Tick when instruction was in execute stage. */
270 Tick executeTick;
271 /* Tick when instruction was marked ready and sent to commit stage. */
272 Tick toCommitTick;
273 /* Tick when instruction was committed. */
274 Tick commitTick;
|
269 /* If instruction was a load, a store, committed. */
270 bool load, store, commit;
| 275 /* If instruction was committed, as against squashed. */
276 bool commit;
|
271 /* List of order dependencies. */
272 std::list<InstSeqNum> robDepList;
273 /* List of physical register RAW dependencies. */
274 std::list<InstSeqNum> physRegDepList;
275 /**
276 * Computational delay after the last dependent inst. completed.
277 * A value of -1 which means instruction has no dependencies.
278 */
279 int64_t compDelay;
280 /* Number of dependents. */
281 uint32_t numDepts;
282 /* The instruction PC for a load, store or non load/store. */
283 Addr pc;
284 /* Request flags in case of a load/store instruction */
285 Request::FlagsType reqFlags;
286 /* Request address in case of a load/store instruction */
287 Addr addr;
288 /* Request size in case of a load/store instruction */
289 unsigned size;
| 277 /* List of order dependencies. */
278 std::list<InstSeqNum> robDepList;
279 /* List of physical register RAW dependencies. */
280 std::list<InstSeqNum> physRegDepList;
281 /**
282 * Computational delay after the last dependent inst. completed.
283 * A value of -1 which means instruction has no dependencies.
284 */
285 int64_t compDelay;
286 /* Number of dependents. */
287 uint32_t numDepts;
288 /* The instruction PC for a load, store or non load/store. */
289 Addr pc;
290 /* Request flags in case of a load/store instruction */
291 Request::FlagsType reqFlags;
292 /* Request address in case of a load/store instruction */
293 Addr addr;
294 /* Request size in case of a load/store instruction */
295 unsigned size;
|
| 296 /** Default Constructor */
297 TraceInfo()
298 : type(Record::INVALID)
299 { }
300 /** Is the record a load */
301 bool isLoad() const { return (type == Record::LOAD); }
302 /** Is the record a store */
303 bool isStore() const { return (type == Record::STORE); }
304 /** Is the record a fetch triggering an Icache request */
305 bool isComp() const { return (type == Record::COMP); }
306 /** Return string specifying the type of the node */
307 const std::string& typeToStr() const;
|
290 /** @} */
291
292 /**
293 * Get the execute tick of the instruction.
294 *
295 * @return Tick when instruction was executed
296 */
297 Tick getExecuteTick() const;
298 };
299
300 /**
301 * The instruction dependency trace containing TraceInfo objects. The
302 * container implemented is sequential as dependencies obey commit
303 * order (program order). For example, if B is dependent on A then B must
304 * be committed after A. Thus records are updated with dependency
305 * information and written to the trace in commit order. This ensures that
306 * when a graph is reconstructed from the trace during replay, all the
307 * dependencies are stored in the graph before the dependent itself is
308 * added. This facilitates creating a tree data structure during replay,
309 * i.e. adding children as records are read from the trace in an efficient
310 * manner.
311 */
312 std::vector<TraceInfo*> depTrace;
313
314 /**
315 * Map where the instruction sequence number is mapped to the pointer to
316 * the TraceInfo object.
317 */
318 std::unordered_map<InstSeqNum, TraceInfo*> traceInfoMap;
319
320 /** Typedef of iterator to the instruction dependency trace. */
321 typedef typename std::vector<TraceInfo*>::iterator depTraceItr;
322
323 /** Typedef of the reverse iterator to the instruction dependency trace. */
324 typedef typename std::reverse_iterator<depTraceItr> depTraceRevItr;
325
326 /**
327 * The maximum distance for a dependency and is set by a top level
328 * level parameter. It must be equal to or greater than the number of
329 * entries in the ROB. This variable is used as the length of the sliding
330 * window for processing the dependency trace.
331 */
332 uint32_t depWindowSize;
333
334 /** Protobuf output stream for data dependency trace */
335 ProtoOutputStream* dataTraceStream;
336
337 /** Protobuf output stream for instruction fetch trace. */
338 ProtoOutputStream* instTraceStream;
339
340 /** Number of instructions after which to enable tracing. */
341 const InstSeqNum startTraceInst;
342
343 /**
344 * Whther the elastic trace listener has been registered for all probes.
345 *
346 * When enabling tracing after a specified number of instructions have
347 * committed, check this to prevent re-registering the listener.
348 */
349 bool allProbesReg;
350
351 /** Pointer to the O3CPU that is this listener's parent a.k.a. manager */
352 FullO3CPU<O3CPUImpl>* cpu;
353
354 /**
355 * Add a record to the dependency trace depTrace which is a sequential
356 * container. A record is inserted per committed instruction and in the same
357 * order as the order in which instructions are committed.
358 *
359 * @param head_inst Pointer to the instruction which is head of the
360 * ROB and ready to commit
361 * @param exec_info_ptr Pointer to InstExecInfo for that instruction
362 * @param commit True if instruction is committed, false if squashed
363 */
364 void addDepTraceRecord(const DynInstPtr &head_inst,
365 InstExecInfo* exec_info_ptr, bool commit);
366
367 /**
368 * Clear entries in the temporary store of execution info objects to free
369 * allocated memory until the present instruction being added to the trace.
370 *
371 * @param head_inst pointer to dynamic instruction
372 */
373 void clearTempStoreUntil(const DynInstPtr head_inst);
374
375 /**
376 * Calculate the computational delay between an instruction and a
377 * subsequent instruction that has an ROB (order) dependency on it
378 *
379 * @param past_record Pointer to instruction
380 *
381 * @param new_record Pointer to subsequent instruction having an ROB
382 * dependency on the instruction pointed to by
383 * past_record
384 */
385 void compDelayRob(TraceInfo* past_record, TraceInfo* new_record);
386
387 /**
388 * Calculate the computational delay between an instruction and a
389 * subsequent instruction that has a Physical Register (data) dependency on
390 * it.
391 *
392 * @param past_record Pointer to instruction
393 *
394 * @param new_record Pointer to subsequent instruction having a Physical
395 * Register dependency on the instruction pointed to
396 * by past_record
397 */
398 void compDelayPhysRegDep(TraceInfo* past_record, TraceInfo* new_record);
399
400 /**
401 * Write out given number of records to the trace starting with the first
402 * record in depTrace and iterating through the trace in sequence. A
403 * record is deleted after it is written.
404 *
405 * @param num_to_write Number of records to write to the trace
406 */
407 void writeDepTrace(uint32_t num_to_write);
408
409 /**
410 * Reverse iterate through the graph, search for a store-after-store or
411 * store-after-load dependency and update the new node's Rob dependency list.
412 *
413 * If a dependency is found, then call the assignRobDep() method that
414 * updates the store with the dependency information. This function is only
415 * called when a new store node is added to the trace.
416 *
417 * @param new_record pointer to new store record
418 * @param find_load_not_store true for searching store-after-load and false
419 * for searching store-after-store dependency
420 */
421 void updateCommitOrderDep(TraceInfo* new_record, bool find_load_not_store);
422
423 /**
424 * Reverse iterate through the graph, search for an issue order dependency
425 * for a new node and update the new node's Rob dependency list.
426 *
427 * If a dependency is found, call the assignRobDep() method that updates
428 * the node with its dependency information. This function is called in
429 * case a new node to be added to the trace is dependency-free or its
430 * dependency got discarded because the dependency was outside the window.
431 *
432 * @param new_record pointer to new record to be added to the trace
433 */
434 void updateIssueOrderDep(TraceInfo* new_record);
435
436 /**
437 * The new_record has an order dependency on a past_record, thus update the
438 * new record's Rob dependency list and increment the number of dependents
439 * of the past record.
440 *
441 * @param new_record pointer to new record
442 * @param past_record pointer to record that new_record has a rob
443 * dependency on
444 */
445 void assignRobDep(TraceInfo* past_record, TraceInfo* new_record);
446
447 /**
448 * Check if past record is a store sent earlier than the execute tick.
449 *
450 * @param past_record pointer to past store
451 * @param execute_tick tick with which to compare past store's commit tick
452 *
453 * @return true if past record is store sent earlier
454 */
455 bool hasStoreCommitted(TraceInfo* past_record, Tick execute_tick) const;
456
457 /**
458 * Check if past record is a load that completed earlier than the execute
459 * tick.
460 *
461 * @param past_record pointer to past load
462 * @param execute_tick tick with which to compare past load's complete
463 * tick
464 *
465 * @return true if past record is load completed earlier
466 */
467 bool hasLoadCompleted(TraceInfo* past_record, Tick execute_tick) const;
468
469 /**
470 * Check if past record is a load sent earlier than the execute tick.
471 *
472 * @param past_record pointer to past load
473 * @param execute_tick tick with which to compare past load's send tick
474 *
475 * @return true if past record is load sent earlier
476 */
477 bool hasLoadBeenSent(TraceInfo* past_record, Tick execute_tick) const;
478
479 /**
480 * Check if past record is a comp node that completed earlier than the
481 * execute tick.
482 *
483 * @param past_record pointer to past comp node
484 * @param execute_tick tick with which to compare past comp node's
485 * completion tick
486 *
487 * @return true if past record is comp completed earlier
488 */
489 bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;
490
491 /** Number of register dependencies recorded during tracing */
492 Stats::Scalar numRegDep;
493
494 /**
495 * Number of stores that got assigned a commit order dependency
496 * on a past load/store.
497 */
498 Stats::Scalar numOrderDepStores;
499
500 /**
501 * Number of load insts that got assigned an issue order dependency
502 * because they were dependency-free.
503 */
504 Stats::Scalar numIssueOrderDepLoads;
505
506 /**
507 * Number of store insts that got assigned an issue order dependency
508 * because they were dependency-free.
509 */
510 Stats::Scalar numIssueOrderDepStores;
511
512 /**
513 * Number of non load/store insts that got assigned an issue order
514 * dependency because they were dependency-free.
515 */
516 Stats::Scalar numIssueOrderDepOther;
517
518 /** Number of filtered nodes */
519 Stats::Scalar numFilteredNodes;
520
521 /** Maximum number of dependents on any instruction */
522 Stats::Scalar maxNumDependents;
523
524 /**
525 * Maximum size of the temporary store mostly useful as a check that it is
526 * not growing
527 */
528 Stats::Scalar maxTempStoreSize;
529
530 /**
531 * Maximum size of the map that holds the last writer to a physical
532 * register.
533 * */
534 Stats::Scalar maxPhysRegDepMapSize;
535
536};
537#endif//__CPU_O3_PROBE_ELASTIC_TRACE_HH__
| 308 /** @} */
309
310 /**
311 * Get the execute tick of the instruction.
312 *
313 * @return Tick when instruction was executed
314 */
315 Tick getExecuteTick() const;
316 };
317
318 /**
319 * The instruction dependency trace containing TraceInfo objects. The
320 * container implemented is sequential as dependencies obey commit
321 * order (program order). For example, if B is dependent on A then B must
322 * be committed after A. Thus records are updated with dependency
323 * information and written to the trace in commit order. This ensures that
324 * when a graph is reconstructed from the trace during replay, all the
325 * dependencies are stored in the graph before the dependent itself is
326 * added. This facilitates creating a tree data structure during replay,
327 * i.e. adding children as records are read from the trace in an efficient
328 * manner.
329 */
330 std::vector<TraceInfo*> depTrace;
331
332 /**
333 * Map where the instruction sequence number is mapped to the pointer to
334 * the TraceInfo object.
335 */
336 std::unordered_map<InstSeqNum, TraceInfo*> traceInfoMap;
337
338 /** Typedef of iterator to the instruction dependency trace. */
339 typedef typename std::vector<TraceInfo*>::iterator depTraceItr;
340
341 /** Typedef of the reverse iterator to the instruction dependency trace. */
342 typedef typename std::reverse_iterator<depTraceItr> depTraceRevItr;
343
344 /**
345 * The maximum distance for a dependency and is set by a top level
346 * level parameter. It must be equal to or greater than the number of
347 * entries in the ROB. This variable is used as the length of the sliding
348 * window for processing the dependency trace.
349 */
350 uint32_t depWindowSize;
351
352 /** Protobuf output stream for data dependency trace */
353 ProtoOutputStream* dataTraceStream;
354
355 /** Protobuf output stream for instruction fetch trace. */
356 ProtoOutputStream* instTraceStream;
357
358 /** Number of instructions after which to enable tracing. */
359 const InstSeqNum startTraceInst;
360
361 /**
362 * Whther the elastic trace listener has been registered for all probes.
363 *
364 * When enabling tracing after a specified number of instructions have
365 * committed, check this to prevent re-registering the listener.
366 */
367 bool allProbesReg;
368
369 /** Pointer to the O3CPU that is this listener's parent a.k.a. manager */
370 FullO3CPU<O3CPUImpl>* cpu;
371
372 /**
373 * Add a record to the dependency trace depTrace which is a sequential
374 * container. A record is inserted per committed instruction and in the same
375 * order as the order in which instructions are committed.
376 *
377 * @param head_inst Pointer to the instruction which is head of the
378 * ROB and ready to commit
379 * @param exec_info_ptr Pointer to InstExecInfo for that instruction
380 * @param commit True if instruction is committed, false if squashed
381 */
382 void addDepTraceRecord(const DynInstPtr &head_inst,
383 InstExecInfo* exec_info_ptr, bool commit);
384
385 /**
386 * Clear entries in the temporary store of execution info objects to free
387 * allocated memory until the present instruction being added to the trace.
388 *
389 * @param head_inst pointer to dynamic instruction
390 */
391 void clearTempStoreUntil(const DynInstPtr head_inst);
392
393 /**
394 * Calculate the computational delay between an instruction and a
395 * subsequent instruction that has an ROB (order) dependency on it
396 *
397 * @param past_record Pointer to instruction
398 *
399 * @param new_record Pointer to subsequent instruction having an ROB
400 * dependency on the instruction pointed to by
401 * past_record
402 */
403 void compDelayRob(TraceInfo* past_record, TraceInfo* new_record);
404
405 /**
406 * Calculate the computational delay between an instruction and a
407 * subsequent instruction that has a Physical Register (data) dependency on
408 * it.
409 *
410 * @param past_record Pointer to instruction
411 *
412 * @param new_record Pointer to subsequent instruction having a Physical
413 * Register dependency on the instruction pointed to
414 * by past_record
415 */
416 void compDelayPhysRegDep(TraceInfo* past_record, TraceInfo* new_record);
417
418 /**
419 * Write out given number of records to the trace starting with the first
420 * record in depTrace and iterating through the trace in sequence. A
421 * record is deleted after it is written.
422 *
423 * @param num_to_write Number of records to write to the trace
424 */
425 void writeDepTrace(uint32_t num_to_write);
426
427 /**
428 * Reverse iterate through the graph, search for a store-after-store or
429 * store-after-load dependency and update the new node's Rob dependency list.
430 *
431 * If a dependency is found, then call the assignRobDep() method that
432 * updates the store with the dependency information. This function is only
433 * called when a new store node is added to the trace.
434 *
435 * @param new_record pointer to new store record
436 * @param find_load_not_store true for searching store-after-load and false
437 * for searching store-after-store dependency
438 */
439 void updateCommitOrderDep(TraceInfo* new_record, bool find_load_not_store);
440
441 /**
442 * Reverse iterate through the graph, search for an issue order dependency
443 * for a new node and update the new node's Rob dependency list.
444 *
445 * If a dependency is found, call the assignRobDep() method that updates
446 * the node with its dependency information. This function is called in
447 * case a new node to be added to the trace is dependency-free or its
448 * dependency got discarded because the dependency was outside the window.
449 *
450 * @param new_record pointer to new record to be added to the trace
451 */
452 void updateIssueOrderDep(TraceInfo* new_record);
453
454 /**
455 * The new_record has an order dependency on a past_record, thus update the
456 * new record's Rob dependency list and increment the number of dependents
457 * of the past record.
458 *
459 * @param new_record pointer to new record
460 * @param past_record pointer to record that new_record has a rob
461 * dependency on
462 */
463 void assignRobDep(TraceInfo* past_record, TraceInfo* new_record);
464
465 /**
466 * Check if past record is a store sent earlier than the execute tick.
467 *
468 * @param past_record pointer to past store
469 * @param execute_tick tick with which to compare past store's commit tick
470 *
471 * @return true if past record is store sent earlier
472 */
473 bool hasStoreCommitted(TraceInfo* past_record, Tick execute_tick) const;
474
475 /**
476 * Check if past record is a load that completed earlier than the execute
477 * tick.
478 *
479 * @param past_record pointer to past load
480 * @param execute_tick tick with which to compare past load's complete
481 * tick
482 *
483 * @return true if past record is load completed earlier
484 */
485 bool hasLoadCompleted(TraceInfo* past_record, Tick execute_tick) const;
486
487 /**
488 * Check if past record is a load sent earlier than the execute tick.
489 *
490 * @param past_record pointer to past load
491 * @param execute_tick tick with which to compare past load's send tick
492 *
493 * @return true if past record is load sent earlier
494 */
495 bool hasLoadBeenSent(TraceInfo* past_record, Tick execute_tick) const;
496
497 /**
498 * Check if past record is a comp node that completed earlier than the
499 * execute tick.
500 *
501 * @param past_record pointer to past comp node
502 * @param execute_tick tick with which to compare past comp node's
503 * completion tick
504 *
505 * @return true if past record is comp completed earlier
506 */
507 bool hasCompCompleted(TraceInfo* past_record, Tick execute_tick) const;
508
509 /** Number of register dependencies recorded during tracing */
510 Stats::Scalar numRegDep;
511
512 /**
513 * Number of stores that got assigned a commit order dependency
514 * on a past load/store.
515 */
516 Stats::Scalar numOrderDepStores;
517
518 /**
519 * Number of load insts that got assigned an issue order dependency
520 * because they were dependency-free.
521 */
522 Stats::Scalar numIssueOrderDepLoads;
523
524 /**
525 * Number of store insts that got assigned an issue order dependency
526 * because they were dependency-free.
527 */
528 Stats::Scalar numIssueOrderDepStores;
529
530 /**
531 * Number of non load/store insts that got assigned an issue order
532 * dependency because they were dependency-free.
533 */
534 Stats::Scalar numIssueOrderDepOther;
535
536 /** Number of filtered nodes */
537 Stats::Scalar numFilteredNodes;
538
539 /** Maximum number of dependents on any instruction */
540 Stats::Scalar maxNumDependents;
541
542 /**
543 * Maximum size of the temporary store mostly useful as a check that it is
544 * not growing
545 */
546 Stats::Scalar maxTempStoreSize;
547
548 /**
549 * Maximum size of the map that holds the last writer to a physical
550 * register.
551 * */
552 Stats::Scalar maxPhysRegDepMapSize;
553
554};
555#endif//__CPU_O3_PROBE_ELASTIC_TRACE_HH__
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