1/*
2 * Copyright (c) 2013 - 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 76 unchanged lines hidden (view full) ---

85 *
86 * The output trace can be read in and played back by the TraceCPU.
87 */
88class ElasticTrace : public ProbeListenerObject
89{
90
91 public:
92 typedef typename O3CPUImpl::DynInstPtr DynInstPtr;
93 typedef typename std::pair<InstSeqNum, PhysRegIndex> SeqNumRegPair;
94
95 /** Trace record types corresponding to instruction node types */
96 typedef ProtoMessage::InstDepRecord::RecordType RecordType;
97 typedef ProtoMessage::InstDepRecord Record;
98
99 /** Constructor */
100 ElasticTrace(const ElasticTraceParams *params);

--- 26 unchanged lines hidden (view full) ---

127 void fetchReqTrace(const RequestPtr &req);
128
129 /**
130 * Populate the execute timestamp field in an InstExecInfo object for an
131 * instruction in flight.
132 *
133 * @param dyn_inst pointer to dynamic instruction in flight
134 */
135 void recordExecTick(const DynInstPtr &dyn_inst);
136
137 /**
138 * Populate the timestamp field in an InstExecInfo object for an
139 * instruction in flight when it is execution is complete and it is ready
140 * to commit.
141 *
142 * @param dyn_inst pointer to dynamic instruction in flight
143 */
144 void recordToCommTick(const DynInstPtr &dyn_inst);
145
146 /**
147 * Record a Read After Write physical register dependency if there has
148 * been a write to the source register and update the physical register
149 * map. For this look up the physRegDepMap with this instruction as the
150 * writer of its destination register. If the dependency falls outside the
151 * window it is assumed as already complete. Duplicate entries are avoided.
152 *
153 * @param dyn_inst pointer to dynamic instruction in flight
154 */
155 void updateRegDep(const DynInstPtr &dyn_inst);
156
157 /**
158 * When an instruction gets squashed the destination register mapped to it
159 * is freed up in the rename stage. Remove the register entry from the
160 * physRegDepMap as well to avoid dependencies on squashed instructions.
161 *
162 * @param inst_reg_pair pair of inst. sequence no. and the register
163 */
164 void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair);
165
166 /**
167 * Add an instruction that is at the head of the ROB and is squashed only
168 * if it is a load and a request was sent for it.
169 *
170 * @param head_inst pointer to dynamic instruction to be squashed
171 */
172 void addSquashedInst(const DynInstPtr &head_inst);
173
174 /**
175 * Add an instruction that is at the head of the ROB and is committed.
176 *
177 * @param head_inst pointer to dynamic instruction to be committed
178 */
179 void addCommittedInst(const DynInstPtr &head_inst);
180
181 /** Register statistics for the elastic trace. */
182 void regStats();
183
184 /** Event to trigger registering this listener for all probe points. */
185 EventFunctionWrapper regEtraceListenersEvent;
186
187 private:

--- 192 unchanged lines hidden (view full) ---

380 * container. A record is inserted per committed instruction and in the same
381 * order as the order in which instructions are committed.
382 *
383 * @param head_inst Pointer to the instruction which is head of the
384 * ROB and ready to commit
385 * @param exec_info_ptr Pointer to InstExecInfo for that instruction
386 * @param commit True if instruction is committed, false if squashed
387 */
388 void addDepTraceRecord(const DynInstPtr &head_inst,
389 InstExecInfo* exec_info_ptr, bool commit);
390
391 /**
392 * Clear entries in the temporary store of execution info objects to free
393 * allocated memory until the present instruction being added to the trace.
394 *
395 * @param head_inst pointer to dynamic instruction
396 */
397 void clearTempStoreUntil(const DynInstPtr head_inst);
398
399 /**
400 * Calculate the computational delay between an instruction and a
401 * subsequent instruction that has an ROB (order) dependency on it
402 *
403 * @param past_record Pointer to instruction
404 *
405 * @param new_record Pointer to subsequent instruction having an ROB

--- 156 unchanged lines hidden ---