mem_dep_unit_impl.hh (8519:ef35ce2bd73f) mem_dep_unit_impl.hh (9444:ab47fe7f03f0)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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109
110 conflictingStores
111 .name(name() + ".conflictingStores")
112 .desc("Number of conflicting stores.");
113}
114
115template <class MemDepPred, class Impl>
116void
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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121
122 conflictingStores
123 .name(name() + ".conflictingStores")
124 .desc("Number of conflicting stores.");
125}
126
127template <class MemDepPred, class Impl>
128void
117MemDepUnit<MemDepPred, Impl>::switchOut()
129MemDepUnit<MemDepPred, Impl>::drainSanityCheck() const
118{
130{
119 assert(instList[0].empty());
120 assert(instsToReplay.empty());
121 assert(memDepHash.empty());
131 assert(instsToReplay.empty());
132 assert(memDepHash.empty());
122 // Clear any state.
123 for (int i = 0; i < Impl::MaxThreads; ++i) {
124 instList[i].clear();
125 }
126 instsToReplay.clear();
127 memDepHash.clear();
133 for (int i = 0; i < Impl::MaxThreads; ++i)
134 assert(instList[i].empty());
135 assert(instsToReplay.empty());
136 assert(memDepHash.empty());
128}
129
130template <class MemDepPred, class Impl>
131void
132MemDepUnit<MemDepPred, Impl>::takeOverFrom()
133{
134 // Be sure to reset all state.
135 loadBarrier = storeBarrier = false;

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138
139template <class MemDepPred, class Impl>
140void
141MemDepUnit<MemDepPred, Impl>::takeOverFrom()
142{
143 // Be sure to reset all state.
144 loadBarrier = storeBarrier = false;

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