mem_dep_unit_impl.hh (8232:b28d06a175be) mem_dep_unit_impl.hh (8515:12420b96b364)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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400template <class MemDepPred, class Impl>
401void
402MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
403{
404 wakeDependents(inst);
405 completed(inst);
406
407 InstSeqNum barr_sn = inst->seqNum;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 391 unchanged lines hidden (view full) ---

400template <class MemDepPred, class Impl>
401void
402MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
403{
404 wakeDependents(inst);
405 completed(inst);
406
407 InstSeqNum barr_sn = inst->seqNum;
408
408 DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
409 inst->seqNum);
409 if (inst->isMemBarrier()) {
410 if (inst->isMemBarrier()) {
410 assert(loadBarrier && storeBarrier);
411 if (loadBarrierSN == barr_sn)
412 loadBarrier = false;
413 if (storeBarrierSN == barr_sn)
414 storeBarrier = false;
415 } else if (inst->isWriteBarrier()) {
411 if (loadBarrierSN == barr_sn)
412 loadBarrier = false;
413 if (storeBarrierSN == barr_sn)
414 storeBarrier = false;
415 } else if (inst->isWriteBarrier()) {
416 assert(storeBarrier);
417 if (storeBarrierSN == barr_sn)
418 storeBarrier = false;
419 }
420}
421
422template <class MemDepPred, class Impl>
423void
424MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)

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475 MemDepHashIt hash_it;
476
477 while (!instList[tid].empty() &&
478 (*squash_it)->seqNum > squashed_num) {
479
480 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
481 (*squash_it)->seqNum);
482
416 if (storeBarrierSN == barr_sn)
417 storeBarrier = false;
418 }
419}
420
421template <class MemDepPred, class Impl>
422void
423MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)

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474 MemDepHashIt hash_it;
475
476 while (!instList[tid].empty() &&
477 (*squash_it)->seqNum > squashed_num) {
478
479 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
480 (*squash_it)->seqNum);
481
482 if ((*squash_it)->seqNum == loadBarrierSN)
483 loadBarrier = false;
484
485 if ((*squash_it)->seqNum == storeBarrierSN)
486 storeBarrier = false;
487
483 hash_it = memDepHash.find((*squash_it)->seqNum);
484
485 assert(hash_it != memDepHash.end());
486
487 (*hash_it).second->squashed = true;
488
489 (*hash_it).second = NULL;
490

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504void
505MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
506 DynInstPtr &violating_load)
507{
508 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
509 " load: %#x, store: %#x\n", violating_load->instAddr(),
510 store_inst->instAddr());
511 // Tell the memory dependence unit of the violation.
488 hash_it = memDepHash.find((*squash_it)->seqNum);
489
490 assert(hash_it != memDepHash.end());
491
492 (*hash_it).second->squashed = true;
493
494 (*hash_it).second = NULL;
495

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509void
510MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
511 DynInstPtr &violating_load)
512{
513 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
514 " load: %#x, store: %#x\n", violating_load->instAddr(),
515 store_inst->instAddr());
516 // Tell the memory dependence unit of the violation.
512 depPred.violation(violating_load->instAddr(), store_inst->instAddr());
517 depPred.violation(store_inst->instAddr(), violating_load->instAddr());
513}
514
515template <class MemDepPred, class Impl>
516void
517MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
518{
519 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
520 inst->instAddr(), inst->seqNum);

--- 58 unchanged lines hidden --- 		518}
519
520template <class MemDepPred, class Impl>
521void
522MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
523{
524 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
525 inst->instAddr(), inst->seqNum);

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