mem_dep_unit_impl.hh (7676:92274350b953) mem_dep_unit_impl.hh (7720:65d338a8dba4)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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166 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
167 loadBarrierSN);
168 producing_store = loadBarrierSN;
169 } else if (inst->isStore() && storeBarrier) {
170 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
171 storeBarrierSN);
172 producing_store = storeBarrierSN;
173 } else {
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 157 unchanged lines hidden (view full) ---

166 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
167 loadBarrierSN);
168 producing_store = loadBarrierSN;
169 } else if (inst->isStore() && storeBarrier) {
170 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
171 storeBarrierSN);
172 producing_store = storeBarrierSN;
173 } else {
174 producing_store = depPred.checkInst(inst->readPC());
174 producing_store = depPred.checkInst(inst->instAddr());
175 }
176
177 MemDepEntryPtr store_entry = NULL;
178
179 // If there is a producing store, try to find the entry.
180 if (producing_store != 0) {
181 DPRINTF(MemDepUnit, "Searching for producer\n");
182 MemDepHashIt hash_it = memDepHash.find(producing_store);
183
184 if (hash_it != memDepHash.end()) {
185 store_entry = (*hash_it).second;
186 DPRINTF(MemDepUnit, "Proucer found\n");
187 }
188 }
189
190 // If no store entry, then instruction can issue as soon as the registers
191 // are ready.
192 if (!store_entry) {
193 DPRINTF(MemDepUnit, "No dependency for inst PC "
175 }
176
177 MemDepEntryPtr store_entry = NULL;
178
179 // If there is a producing store, try to find the entry.
180 if (producing_store != 0) {
181 DPRINTF(MemDepUnit, "Searching for producer\n");
182 MemDepHashIt hash_it = memDepHash.find(producing_store);
183
184 if (hash_it != memDepHash.end()) {
185 store_entry = (*hash_it).second;
186 DPRINTF(MemDepUnit, "Proucer found\n");
187 }
188 }
189
190 // If no store entry, then instruction can issue as soon as the registers
191 // are ready.
192 if (!store_entry) {
193 DPRINTF(MemDepUnit, "No dependency for inst PC "
194 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
194 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
195
196 inst_entry->memDepReady = true;
197
198 if (inst->readyToIssue()) {
199 inst_entry->regsReady = true;
200
201 moveToReady(inst_entry);
202 }
203 } else {
204 // Otherwise make the instruction dependent on the store/barrier.
205 DPRINTF(MemDepUnit, "Adding to dependency list; "
195
196 inst_entry->memDepReady = true;
197
198 if (inst->readyToIssue()) {
199 inst_entry->regsReady = true;
200
201 moveToReady(inst_entry);
202 }
203 } else {
204 // Otherwise make the instruction dependent on the store/barrier.
205 DPRINTF(MemDepUnit, "Adding to dependency list; "
206 "inst PC %#x is dependent on [sn:%lli].\n",
207 inst->readPC(), producing_store);
206 "inst PC %s is dependent on [sn:%lli].\n",
207 inst->pcState(), producing_store);
208
209 if (inst->readyToIssue()) {
210 inst_entry->regsReady = true;
211 }
212
213 // Clear the bit saying this instruction can issue.
214 inst->clearCanIssue();
215
216 // Add this instruction to the list of dependents.
217 store_entry->dependInsts.push_back(inst_entry);
218
219 if (inst->isLoad()) {
220 ++conflictingLoads;
221 } else {
222 ++conflictingStores;
223 }
224 }
225
226 if (inst->isStore()) {
208
209 if (inst->readyToIssue()) {
210 inst_entry->regsReady = true;
211 }
212
213 // Clear the bit saying this instruction can issue.
214 inst->clearCanIssue();
215
216 // Add this instruction to the list of dependents.
217 store_entry->dependInsts.push_back(inst_entry);
218
219 if (inst->isLoad()) {
220 ++conflictingLoads;
221 } else {
222 ++conflictingStores;
223 }
224 }
225
226 if (inst->isStore()) {
227 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
228 inst->readPC(), inst->seqNum);
227 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
228 inst->pcState(), inst->seqNum);
229
229
230 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
230 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
231
232 ++insertedStores;
233 } else if (inst->isLoad()) {
234 ++insertedLoads;
235 } else {
236 panic("Unknown type! (most likely a barrier).");
237 }
238}

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255 // Add the instruction to the list.
256 instList[tid].push_back(inst);
257
258 inst_entry->listIt = --(instList[tid].end());
259
260 // Might want to turn this part into an inline function or something.
261 // It's shared between both insert functions.
262 if (inst->isStore()) {
231
232 ++insertedStores;
233 } else if (inst->isLoad()) {
234 ++insertedLoads;
235 } else {
236 panic("Unknown type! (most likely a barrier).");
237 }
238}

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255 // Add the instruction to the list.
256 instList[tid].push_back(inst);
257
258 inst_entry->listIt = --(instList[tid].end());
259
260 // Might want to turn this part into an inline function or something.
261 // It's shared between both insert functions.
262 if (inst->isStore()) {
263 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
264 inst->readPC(), inst->seqNum);
263 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
264 inst->pcState(), inst->seqNum);
265
265
266 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
266 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
267
268 ++insertedStores;
269 } else if (inst->isLoad()) {
270 ++insertedLoads;
271 } else {
272 panic("Unknown type! (most likely a barrier).");
273 }
274}

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308 inst_entry->listIt = --(instList[tid].end());
309}
310
311template <class MemDepPred, class Impl>
312void
313MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
314{
315 DPRINTF(MemDepUnit, "Marking registers as ready for "
267
268 ++insertedStores;
269 } else if (inst->isLoad()) {
270 ++insertedLoads;
271 } else {
272 panic("Unknown type! (most likely a barrier).");
273 }
274}

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308 inst_entry->listIt = --(instList[tid].end());
309}
310
311template <class MemDepPred, class Impl>
312void
313MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
314{
315 DPRINTF(MemDepUnit, "Marking registers as ready for "
316 "instruction PC %#x [sn:%lli].\n",
317 inst->readPC(), inst->seqNum);
316 "instruction PC %s [sn:%lli].\n",
317 inst->pcState(), inst->seqNum);
318
319 MemDepEntryPtr inst_entry = findInHash(inst);
320
321 inst_entry->regsReady = true;
322
323 if (inst_entry->memDepReady) {
324 DPRINTF(MemDepUnit, "Instruction has its memory "
325 "dependencies resolved, adding it to the ready list.\n");

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331 }
332}
333
334template <class MemDepPred, class Impl>
335void
336MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
337{
338 DPRINTF(MemDepUnit, "Marking non speculative "
318
319 MemDepEntryPtr inst_entry = findInHash(inst);
320
321 inst_entry->regsReady = true;
322
323 if (inst_entry->memDepReady) {
324 DPRINTF(MemDepUnit, "Instruction has its memory "
325 "dependencies resolved, adding it to the ready list.\n");

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331 }
332}
333
334template <class MemDepPred, class Impl>
335void
336MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
337{
338 DPRINTF(MemDepUnit, "Marking non speculative "
339 "instruction PC %#x as ready [sn:%lli].\n",
340 inst->readPC(), inst->seqNum);
339 "instruction PC %s as ready [sn:%lli].\n",
340 inst->pcState(), inst->seqNum);
341
342 MemDepEntryPtr inst_entry = findInHash(inst);
343
344 moveToReady(inst_entry);
345}
346
347template <class MemDepPred, class Impl>
348void

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358 DynInstPtr temp_inst;
359
360 // For now this replay function replays all waiting memory ops.
361 while (!instsToReplay.empty()) {
362 temp_inst = instsToReplay.front();
363
364 MemDepEntryPtr inst_entry = findInHash(temp_inst);
365
341
342 MemDepEntryPtr inst_entry = findInHash(inst);
343
344 moveToReady(inst_entry);
345}
346
347template <class MemDepPred, class Impl>
348void

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358 DynInstPtr temp_inst;
359
360 // For now this replay function replays all waiting memory ops.
361 while (!instsToReplay.empty()) {
362 temp_inst = instsToReplay.front();
363
364 MemDepEntryPtr inst_entry = findInHash(temp_inst);
365
366 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
367 "[sn:%lli].\n",
368 temp_inst->readPC(), temp_inst->seqNum);
366 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
367 temp_inst->pcState(), temp_inst->seqNum);
369
370 moveToReady(inst_entry);
371
372 instsToReplay.pop_front();
373 }
374}
375
376template <class MemDepPred, class Impl>
377void
378MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
379{
368
369 moveToReady(inst_entry);
370
371 instsToReplay.pop_front();
372 }
373}
374
375template <class MemDepPred, class Impl>
376void
377MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
378{
380 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
381 "[sn:%lli].\n",
382 inst->readPC(), inst->seqNum);
379 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
380 inst->pcState(), inst->seqNum);
383
384 ThreadID tid = inst->threadNumber;
385
386 // Remove the instruction from the hash and the list.
387 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
388
389 assert(hash_it != memDepHash.end());
390

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502}
503
504template <class MemDepPred, class Impl>
505void
506MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
507 DynInstPtr &violating_load)
508{
509 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
381
382 ThreadID tid = inst->threadNumber;
383
384 // Remove the instruction from the hash and the list.
385 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
386
387 assert(hash_it != memDepHash.end());
388

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500}
501
502template <class MemDepPred, class Impl>
503void
504MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
505 DynInstPtr &violating_load)
506{
507 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
510 " load: %#x, store: %#x\n", violating_load->readPC(),
511 store_inst->readPC());
508 " load: %#x, store: %#x\n", violating_load->instAddr(),
509 store_inst->instAddr());
512 // Tell the memory dependence unit of the violation.
510 // Tell the memory dependence unit of the violation.
513 depPred.violation(violating_load->readPC(), store_inst->readPC());
511 depPred.violation(violating_load->instAddr(), store_inst->instAddr());
514}
515
516template <class MemDepPred, class Impl>
517void
518MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
519{
520 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
512}
513
514template <class MemDepPred, class Impl>
515void
516MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
517{
518 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
521 inst->readPC(), inst->seqNum);
519 inst->instAddr(), inst->seqNum);
522
520
523 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
521 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
524}
525
526template <class MemDepPred, class Impl>
527inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
528MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
529{
530 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
531

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554 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
555 cprintf("Instruction list %i size: %i\n",
556 tid, instList[tid].size());
557
558 ListIt inst_list_it = instList[tid].begin();
559 int num = 0;
560
561 while (inst_list_it != instList[tid].end()) {
522}
523
524template <class MemDepPred, class Impl>
525inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
526MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
527{
528 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
529

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552 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
553 cprintf("Instruction list %i size: %i\n",
554 tid, instList[tid].size());
555
556 ListIt inst_list_it = instList[tid].begin();
557 int num = 0;
558
559 while (inst_list_it != instList[tid].end()) {
562 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
560 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
563 "Squashed:%i\n\n",
561 "Squashed:%i\n\n",
564 num, (*inst_list_it)->readPC(),
562 num, (*inst_list_it)->pcState(),
565 (*inst_list_it)->seqNum,
566 (*inst_list_it)->threadNumber,
567 (*inst_list_it)->isIssued(),
568 (*inst_list_it)->isSquashed());
569 inst_list_it++;
570 ++num;
571 }
572 }
573
574 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
575
576#ifdef DEBUG
577 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
578#endif
579}
563 (*inst_list_it)->seqNum,
564 (*inst_list_it)->threadNumber,
565 (*inst_list_it)->isIssued(),
566 (*inst_list_it)->isSquashed());
567 inst_list_it++;
568 ++num;
569 }
570 }
571
572 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
573
574#ifdef DEBUG
575 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
576#endif
577}