mem_dep_unit_impl.hh (2670:9107b8bd08cd) mem_dep_unit_impl.hh (2674:6d4afef73a20)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102 .name(name() + ".memDep.conflictingStores")
103 .desc("Number of conflicting stores.");
104}
105
106template <class MemDepPred, class Impl>
107void
108MemDepUnit<MemDepPred, Impl>::switchOut()
109{
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102 .name(name() + ".memDep.conflictingStores")
103 .desc("Number of conflicting stores.");
104}
105
106template <class MemDepPred, class Impl>
107void
108MemDepUnit<MemDepPred, Impl>::switchOut()
109{
110 // Clear any state.
110 for (int i = 0; i < Impl::MaxThreads; ++i) {
111 instList[i].clear();
112 }
113 instsToReplay.clear();
114 memDepHash.clear();
115}
116
117template <class MemDepPred, class Impl>
118void
119MemDepUnit<MemDepPred, Impl>::takeOverFrom()
120{
111 for (int i = 0; i < Impl::MaxThreads; ++i) {
112 instList[i].clear();
113 }
114 instsToReplay.clear();
115 memDepHash.clear();
116}
117
118template <class MemDepPred, class Impl>
119void
120MemDepUnit<MemDepPred, Impl>::takeOverFrom()
121{
122 // Be sure to reset all state.
121 loadBarrier = storeBarrier = false;
122 loadBarrierSN = storeBarrierSN = 0;
123 depPred.clear();
124}
125
126template <class MemDepPred, class Impl>
127void
128MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)

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143 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
144 MemDepEntry::memdep_insert++;
145
146 instList[tid].push_back(inst);
147
148 inst_entry->listIt = --(instList[tid].end());
149
150 // Check any barriers and the dependence predictor for any
123 loadBarrier = storeBarrier = false;
124 loadBarrierSN = storeBarrierSN = 0;
125 depPred.clear();
126}
127
128template <class MemDepPred, class Impl>
129void
130MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)

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145 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
146 MemDepEntry::memdep_insert++;
147
148 instList[tid].push_back(inst);
149
150 inst_entry->listIt = --(instList[tid].end());
151
152 // Check any barriers and the dependence predictor for any
151 // producing stores.
153 // producing memrefs/stores.
152 InstSeqNum producing_store;
153 if (inst->isLoad() && loadBarrier) {
154 producing_store = loadBarrierSN;
155 } else if (inst->isStore() && storeBarrier) {
156 producing_store = storeBarrierSN;
157 } else {
158 producing_store = depPred.checkInst(inst->readPC());
159 }

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250 }
251}
252
253template <class MemDepPred, class Impl>
254void
255MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
256{
257 InstSeqNum barr_sn = barr_inst->seqNum;
154 InstSeqNum producing_store;
155 if (inst->isLoad() && loadBarrier) {
156 producing_store = loadBarrierSN;
157 } else if (inst->isStore() && storeBarrier) {
158 producing_store = storeBarrierSN;
159 } else {
160 producing_store = depPred.checkInst(inst->readPC());
161 }

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252 }
253}
254
255template <class MemDepPred, class Impl>
256void
257MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
258{
259 InstSeqNum barr_sn = barr_inst->seqNum;
260 // Memory barriers block loads and stores, write barriers only stores.
258 if (barr_inst->isMemBarrier()) {
259 loadBarrier = true;
260 loadBarrierSN = barr_sn;
261 storeBarrier = true;
262 storeBarrierSN = barr_sn;
263 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
264 } else if (barr_inst->isWriteBarrier()) {
265 storeBarrier = true;

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327
328template <class MemDepPred, class Impl>
329void
330MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
331{
332 DynInstPtr temp_inst;
333 bool found_inst = false;
334
261 if (barr_inst->isMemBarrier()) {
262 loadBarrier = true;
263 loadBarrierSN = barr_sn;
264 storeBarrier = true;
265 storeBarrierSN = barr_sn;
266 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
267 } else if (barr_inst->isWriteBarrier()) {
268 storeBarrier = true;

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330
331template <class MemDepPred, class Impl>
332void
333MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
334{
335 DynInstPtr temp_inst;
336 bool found_inst = false;
337
338 // For now this replay function replays all waiting memory ops.
335 while (!instsToReplay.empty()) {
336 temp_inst = instsToReplay.front();
337
338 MemDepEntryPtr inst_entry = findInHash(temp_inst);
339
340 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
341 "[sn:%lli].\n",
342 temp_inst->readPC(), temp_inst->seqNum);

--- 211 unchanged lines hidden --- 		339 while (!instsToReplay.empty()) {
340 temp_inst = instsToReplay.front();
341
342 MemDepEntryPtr inst_entry = findInHash(temp_inst);
343
344 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
345 "[sn:%lli].\n",
346 temp_inst->readPC(), temp_inst->seqNum);

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