mem_dep_unit_impl.hh (2665:a124942bacb8) mem_dep_unit_impl.hh (2670:9107b8bd08cd)
1/*
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

--- 14 unchanged lines hidden (view full) ---

25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

--- 14 unchanged lines hidden (view full) ---

25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
33#include "cpu/o3/mem_dep_unit.hh"
34
35template <class MemDepPred, class Impl>
34#include "cpu/o3/mem_dep_unit.hh"
35
36template <class MemDepPred, class Impl>
36MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)
37 : depPred(params.SSITSize, params.LFSTSize)
37MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
38 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
39 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
38{
40{
39 DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n");
41 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
40}
41
42template <class MemDepPred, class Impl>
42}
43
44template <class MemDepPred, class Impl>
45MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
46{
47 for (int tid=0; tid < Impl::MaxThreads; tid++) {
48
49 ListIt inst_list_it = instList[tid].begin();
50
51 MemDepHashIt hash_it;
52
53 while (!instList[tid].empty()) {
54 hash_it = memDepHash.find((*inst_list_it)->seqNum);
55
56 assert(hash_it != memDepHash.end());
57
58 memDepHash.erase(hash_it);
59
60 instList[tid].erase(inst_list_it++);
61 }
62 }
63
64 assert(MemDepEntry::memdep_count == 0);
65}
66
67template <class MemDepPred, class Impl>
68std::string
69MemDepUnit<MemDepPred, Impl>::name() const
70{
71 return "memdepunit";
72}
73
74template <class MemDepPred, class Impl>
43void
75void
76MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
77{
78 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
79
80 id = tid;
81
82 depPred.init(params->SSITSize, params->LFSTSize);
83}
84
85template <class MemDepPred, class Impl>
86void
44MemDepUnit<MemDepPred, Impl>::regStats()
45{
46 insertedLoads
47 .name(name() + ".memDep.insertedLoads")
48 .desc("Number of loads inserted to the mem dependence unit.");
49
50 insertedStores
51 .name(name() + ".memDep.insertedStores")

--- 5 unchanged lines hidden (view full) ---

57
58 conflictingStores
59 .name(name() + ".memDep.conflictingStores")
60 .desc("Number of conflicting stores.");
61}
62
63template <class MemDepPred, class Impl>
64void
87MemDepUnit<MemDepPred, Impl>::regStats()
88{
89 insertedLoads
90 .name(name() + ".memDep.insertedLoads")
91 .desc("Number of loads inserted to the mem dependence unit.");
92
93 insertedStores
94 .name(name() + ".memDep.insertedStores")

--- 5 unchanged lines hidden (view full) ---

100
101 conflictingStores
102 .name(name() + ".memDep.conflictingStores")
103 .desc("Number of conflicting stores.");
104}
105
106template <class MemDepPred, class Impl>
107void
108MemDepUnit<MemDepPred, Impl>::switchOut()
109{
110 for (int i = 0; i < Impl::MaxThreads; ++i) {
111 instList[i].clear();
112 }
113 instsToReplay.clear();
114 memDepHash.clear();
115}
116
117template <class MemDepPred, class Impl>
118void
119MemDepUnit<MemDepPred, Impl>::takeOverFrom()
120{
121 loadBarrier = storeBarrier = false;
122 loadBarrierSN = storeBarrierSN = 0;
123 depPred.clear();
124}
125
126template <class MemDepPred, class Impl>
127void
128MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
129{
130 iqPtr = iq_ptr;
131}
132
133template <class MemDepPred, class Impl>
134void
65MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
66{
135MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
136{
67 InstSeqNum inst_seq_num = inst->seqNum;
137 unsigned tid = inst->threadNumber;
68
138
69 Dependency unresolved_dependencies(inst_seq_num);
139 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
70
140
71 InstSeqNum producing_store = depPred.checkInst(inst->readPC());
141 // Add the MemDepEntry to the hash.
142 memDepHash.insert(
143 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
144 MemDepEntry::memdep_insert++;
72
145
73 if (producing_store == 0 ||
74 storeDependents.find(producing_store) == storeDependents.end()) {
146 instList[tid].push_back(inst);
75
147
76 DPRINTF(MemDepUnit, "MemDepUnit: No dependency for inst PC "
77 "%#x.\n", inst->readPC());
148 inst_entry->listIt = --(instList[tid].end());
78
149
79 unresolved_dependencies.storeDep = storeDependents.end();
150 // Check any barriers and the dependence predictor for any
151 // producing stores.
152 InstSeqNum producing_store;
153 if (inst->isLoad() && loadBarrier) {
154 producing_store = loadBarrierSN;
155 } else if (inst->isStore() && storeBarrier) {
156 producing_store = storeBarrierSN;
157 } else {
158 producing_store = depPred.checkInst(inst->readPC());
159 }
80
160
161 MemDepEntryPtr store_entry = NULL;
162
163 // If there is a producing store, try to find the entry.
164 if (producing_store != 0) {
165 MemDepHashIt hash_it = memDepHash.find(producing_store);
166
167 if (hash_it != memDepHash.end()) {
168 store_entry = (*hash_it).second;
169 }
170 }
171
172 // If no store entry, then instruction can issue as soon as the registers
173 // are ready.
174 if (!store_entry) {
175 DPRINTF(MemDepUnit, "No dependency for inst PC "
176 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
177
178 inst_entry->memDepReady = true;
179
81 if (inst->readyToIssue()) {
180 if (inst->readyToIssue()) {
82 readyInsts.insert(inst_seq_num);
83 } else {
84 unresolved_dependencies.memDepReady = true;
181 inst_entry->regsReady = true;
85
182
86 waitingInsts.insert(unresolved_dependencies);
183 moveToReady(inst_entry);
87 }
88 } else {
184 }
185 } else {
89 DPRINTF(MemDepUnit, "MemDepUnit: Adding to dependency list; "
90 "inst PC %#x is dependent on seq num %i.\n",
186 // Otherwise make the instruction dependent on the store/barrier.
187 DPRINTF(MemDepUnit, "Adding to dependency list; "
188 "inst PC %#x is dependent on [sn:%lli].\n",
91 inst->readPC(), producing_store);
92
93 if (inst->readyToIssue()) {
189 inst->readPC(), producing_store);
190
191 if (inst->readyToIssue()) {
94 unresolved_dependencies.regsReady = true;
192 inst_entry->regsReady = true;
95 }
96
193 }
194
97 // Find the store that this instruction is dependent on.
98 sd_it_t store_loc = storeDependents.find(producing_store);
99
100 assert(store_loc != storeDependents.end());
101
102 // Record the location of the store that this instruction is
103 // dependent on.
104 unresolved_dependencies.storeDep = store_loc;
105
106 // If it's not already ready, then add it to the renamed
107 // list and the dependencies.
108 dep_it_t inst_loc =
109 (waitingInsts.insert(unresolved_dependencies)).first;
110
111 // Add this instruction to the list of dependents.
195 // Add this instruction to the list of dependents.
112 (*store_loc).second.push_back(inst_loc);
196 store_entry->dependInsts.push_back(inst_entry);
113
197
114 assert(!(*store_loc).second.empty());
115
116 if (inst->isLoad()) {
117 ++conflictingLoads;
118 } else {
119 ++conflictingStores;
120 }
121 }
122
123 if (inst->isStore()) {
198 if (inst->isLoad()) {
199 ++conflictingLoads;
200 } else {
201 ++conflictingStores;
202 }
203 }
204
205 if (inst->isStore()) {
124 DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
125 inst->readPC());
206 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
207 inst->readPC(), inst->seqNum);
126
208
127 depPred.insertStore(inst->readPC(), inst_seq_num);
209 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
128
210
129 // Make sure this store isn't already in this list.
130 assert(storeDependents.find(inst_seq_num) == storeDependents.end());
131
132 // Put a dependency entry in at the store's sequence number.
133 // Uh, not sure how this works...I want to create an entry but
134 // I don't have anything to put into the value yet.
135 storeDependents[inst_seq_num];
136
137 assert(storeDependents.size() != 0);
138
139 ++insertedStores;
211 ++insertedStores;
140
141 } else if (inst->isLoad()) {
142 ++insertedLoads;
143 } else {
212 } else if (inst->isLoad()) {
213 ++insertedLoads;
214 } else {
144 panic("MemDepUnit: Unknown type! (most likely a barrier).");
215 panic("Unknown type! (most likely a barrier).");
145 }
216 }
146
147 memInsts[inst_seq_num] = inst;
148}
149
150template <class MemDepPred, class Impl>
151void
152MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
153{
217}
218
219template <class MemDepPred, class Impl>
220void
221MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
222{
154 InstSeqNum inst_seq_num = inst->seqNum;
223 unsigned tid = inst->threadNumber;
155
224
156 Dependency non_spec_inst(inst_seq_num);
225 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
157
226
158 non_spec_inst.storeDep = storeDependents.end();
227 // Insert the MemDepEntry into the hash.
228 memDepHash.insert(
229 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
230 MemDepEntry::memdep_insert++;
159
231
160 waitingInsts.insert(non_spec_inst);
232 // Add the instruction to the list.
233 instList[tid].push_back(inst);
161
234
235 inst_entry->listIt = --(instList[tid].end());
236
162 // Might want to turn this part into an inline function or something.
163 // It's shared between both insert functions.
164 if (inst->isStore()) {
237 // Might want to turn this part into an inline function or something.
238 // It's shared between both insert functions.
239 if (inst->isStore()) {
165 DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
166 inst->readPC());
240 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
241 inst->readPC(), inst->seqNum);
167
242
168 depPred.insertStore(inst->readPC(), inst_seq_num);
243 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
169
244
170 // Make sure this store isn't already in this list.
171 assert(storeDependents.find(inst_seq_num) == storeDependents.end());
172
173 // Put a dependency entry in at the store's sequence number.
174 // Uh, not sure how this works...I want to create an entry but
175 // I don't have anything to put into the value yet.
176 storeDependents[inst_seq_num];
177
178 assert(storeDependents.size() != 0);
179
180 ++insertedStores;
245 ++insertedStores;
181
182 } else if (inst->isLoad()) {
183 ++insertedLoads;
184 } else {
246 } else if (inst->isLoad()) {
247 ++insertedLoads;
248 } else {
185 panic("MemDepUnit: Unknown type! (most likely a barrier).");
249 panic("Unknown type! (most likely a barrier).");
186 }
250 }
187
188 memInsts[inst_seq_num] = inst;
189}
190
191template <class MemDepPred, class Impl>
251}
252
253template <class MemDepPred, class Impl>
192typename Impl::DynInstPtr &
193MemDepUnit<MemDepPred, Impl>::top()
254void
255MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
194{
256{
195 topInst = memInsts.find( (*readyInsts.begin()) );
257 InstSeqNum barr_sn = barr_inst->seqNum;
258 if (barr_inst->isMemBarrier()) {
259 loadBarrier = true;
260 loadBarrierSN = barr_sn;
261 storeBarrier = true;
262 storeBarrierSN = barr_sn;
263 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
264 } else if (barr_inst->isWriteBarrier()) {
265 storeBarrier = true;
266 storeBarrierSN = barr_sn;
267 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
268 }
196
269
197 DPRINTF(MemDepUnit, "MemDepUnit: Top instruction is PC %#x.\n",
198 (*topInst).second->readPC());
270 unsigned tid = barr_inst->threadNumber;
199
271
200 return (*topInst).second;
272 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
273
274 // Add the MemDepEntry to the hash.
275 memDepHash.insert(
276 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
277 MemDepEntry::memdep_insert++;
278
279 // Add the instruction to the instruction list.
280 instList[tid].push_back(barr_inst);
281
282 inst_entry->listIt = --(instList[tid].end());
201}
202
203template <class MemDepPred, class Impl>
204void
283}
284
285template <class MemDepPred, class Impl>
286void
205MemDepUnit<MemDepPred, Impl>::pop()
287MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
206{
288{
207 DPRINTF(MemDepUnit, "MemDepUnit: Removing instruction PC %#x.\n",
208 (*topInst).second->readPC());
289 DPRINTF(MemDepUnit, "Marking registers as ready for "
290 "instruction PC %#x [sn:%lli].\n",
291 inst->readPC(), inst->seqNum);
209
292
210 wakeDependents((*topInst).second);
293 MemDepEntryPtr inst_entry = findInHash(inst);
211
294
212 issue((*topInst).second);
295 inst_entry->regsReady = true;
213
296
214 memInsts.erase(topInst);
297 if (inst_entry->memDepReady) {
298 DPRINTF(MemDepUnit, "Instruction has its memory "
299 "dependencies resolved, adding it to the ready list.\n");
215
300
216 topInst = memInsts.end();
301 moveToReady(inst_entry);
302 } else {
303 DPRINTF(MemDepUnit, "Instruction still waiting on "
304 "memory dependency.\n");
305 }
217}
218
219template <class MemDepPred, class Impl>
220void
306}
307
308template <class MemDepPred, class Impl>
309void
221MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
310MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
222{
311{
223 DPRINTF(MemDepUnit, "MemDepUnit: Marking registers as ready for "
224 "instruction PC %#x.\n",
225 inst->readPC());
312 DPRINTF(MemDepUnit, "Marking non speculative "
313 "instruction PC %#x as ready [sn:%lli].\n",
314 inst->readPC(), inst->seqNum);
226
315
227 InstSeqNum inst_seq_num = inst->seqNum;
316 MemDepEntryPtr inst_entry = findInHash(inst);
228
317
229 Dependency inst_to_find(inst_seq_num);
318 moveToReady(inst_entry);
319}
230
320
231 dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
321template <class MemDepPred, class Impl>
322void
323MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
324{
325 instsToReplay.push_back(inst);
326}
232
327
233 assert(waiting_inst != waitingInsts.end());
328template <class MemDepPred, class Impl>
329void
330MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
331{
332 DynInstPtr temp_inst;
333 bool found_inst = false;
234
334
235 if ((*waiting_inst).memDepReady) {
236 DPRINTF(MemDepUnit, "MemDepUnit: Instruction has its memory "
237 "dependencies resolved, adding it to the ready list.\n");
335 while (!instsToReplay.empty()) {
336 temp_inst = instsToReplay.front();
238
337
239 moveToReady(waiting_inst);
240 } else {
241 DPRINTF(MemDepUnit, "MemDepUnit: Instruction still waiting on "
242 "memory dependency.\n");
338 MemDepEntryPtr inst_entry = findInHash(temp_inst);
243
339
244 (*waiting_inst).regsReady = true;
340 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
341 "[sn:%lli].\n",
342 temp_inst->readPC(), temp_inst->seqNum);
343
344 moveToReady(inst_entry);
345
346 if (temp_inst == inst) {
347 found_inst = true;
348 }
349
350 instsToReplay.pop_front();
245 }
351 }
352
353 assert(found_inst);
246}
247
248template <class MemDepPred, class Impl>
249void
354}
355
356template <class MemDepPred, class Impl>
357void
250MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
358MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
251{
359{
252 DPRINTF(MemDepUnit, "MemDepUnit: Marking non speculative "
253 "instruction PC %#x as ready.\n",
254 inst->readPC());
360 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
361 "[sn:%lli].\n",
362 inst->readPC(), inst->seqNum);
255
363
256 InstSeqNum inst_seq_num = inst->seqNum;
364 unsigned tid = inst->threadNumber;
257
365
258 Dependency inst_to_find(inst_seq_num);
366 // Remove the instruction from the hash and the list.
367 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
259
368
260 dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
369 assert(hash_it != memDepHash.end());
261
370
262 assert(waiting_inst != waitingInsts.end());
371 instList[tid].erase((*hash_it).second->listIt);
263
372
264 moveToReady(waiting_inst);
373 (*hash_it).second = NULL;
374
375 memDepHash.erase(hash_it);
376 MemDepEntry::memdep_erase++;
265}
266
267template <class MemDepPred, class Impl>
268void
377}
378
379template <class MemDepPred, class Impl>
380void
269MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
381MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
270{
382{
271 assert(readyInsts.find(inst->seqNum) != readyInsts.end());
383 wakeDependents(inst);
384 completed(inst);
272
385
273 DPRINTF(MemDepUnit, "MemDepUnit: Issuing instruction PC %#x.\n",
274 inst->readPC());
386 InstSeqNum barr_sn = inst->seqNum;
275
387
276 // Remove the instruction from the ready list.
277 readyInsts.erase(inst->seqNum);
278
279 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
388 if (inst->isMemBarrier()) {
389 assert(loadBarrier && storeBarrier);
390 if (loadBarrierSN == barr_sn)
391 loadBarrier = false;
392 if (storeBarrierSN == barr_sn)
393 storeBarrier = false;
394 } else if (inst->isWriteBarrier()) {
395 assert(storeBarrier);
396 if (storeBarrierSN == barr_sn)
397 storeBarrier = false;
398 }
280}
281
282template <class MemDepPred, class Impl>
283void
284MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
285{
399}
400
401template <class MemDepPred, class Impl>
402void
403MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
404{
286 // Only stores have dependents.
287 if (!inst->isStore()) {
405 // Only stores and barriers have dependents.
406 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
288 return;
289 }
290
407 return;
408 }
409
291 // Wake any dependencies.
292 sd_it_t sd_it = storeDependents.find(inst->seqNum);
410 MemDepEntryPtr inst_entry = findInHash(inst);
293
411
294 // If there's no entry, then return. Really there should only be
295 // no entry if the instruction is a load.
296 if (sd_it == storeDependents.end()) {
297 DPRINTF(MemDepUnit, "MemDepUnit: Instruction PC %#x, sequence "
298 "number %i has no dependents.\n",
299 inst->readPC(), inst->seqNum);
412 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
413 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
300
414
301 return;
302 }
303
304 for (int i = 0; i < (*sd_it).second.size(); ++i ) {
305 dep_it_t woken_inst = (*sd_it).second[i];
306
307 DPRINTF(MemDepUnit, "MemDepUnit: Waking up a dependent inst, "
308 "sequence number %i.\n",
309 (*woken_inst).seqNum);
310#if 0
311 // Should we have reached instructions that are actually squashed,
312 // there will be no more useful instructions in this dependency
313 // list. Break out early.
314 if (waitingInsts.find(woken_inst) == waitingInsts.end()) {
315 DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x "
316 "are squashed, starting at SN %i. Breaking early.\n",
317 inst->readPC(), woken_inst);
318 break;
415 if (!woken_inst->inst) {
416 // Potentially removed mem dep entries could be on this list
417 continue;
319 }
418 }
320#endif
321
419
322 if ((*woken_inst).regsReady) {
420 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
421 "[sn:%lli].\n",
422 woken_inst->inst->seqNum);
423
424 if (woken_inst->regsReady && !woken_inst->squashed) {
323 moveToReady(woken_inst);
324 } else {
425 moveToReady(woken_inst);
426 } else {
325 (*woken_inst).memDepReady = true;
427 woken_inst->memDepReady = true;
326 }
327 }
328
428 }
429 }
430
329 storeDependents.erase(sd_it);
431 inst_entry->dependInsts.clear();
330}
331
332template <class MemDepPred, class Impl>
333void
432}
433
434template <class MemDepPred, class Impl>
435void
334MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num)
436MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
437 unsigned tid)
335{
438{
336
337 if (!waitingInsts.empty()) {
338 dep_it_t waiting_it = waitingInsts.end();
339
340 --waiting_it;
341
342 // Remove entries from the renamed list as long as we haven't reached
343 // the end and the entries continue to be younger than the squashed.
344 while (!waitingInsts.empty() &&
345 (*waiting_it).seqNum > squashed_num)
346 {
347 if (!(*waiting_it).memDepReady &&
348 (*waiting_it).storeDep != storeDependents.end()) {
349 sd_it_t sd_it = (*waiting_it).storeDep;
350
351 // Make sure the iterator that the store has pointing
352 // back is actually to this instruction.
353 assert((*sd_it).second.back() == waiting_it);
354
355 // Now remove this from the store's list of dependent
356 // instructions.
357 (*sd_it).second.pop_back();
439 if (!instsToReplay.empty()) {
440 ListIt replay_it = instsToReplay.begin();
441 while (replay_it != instsToReplay.end()) {
442 if ((*replay_it)->threadNumber == tid &&
443 (*replay_it)->seqNum > squashed_num) {
444 instsToReplay.erase(replay_it++);
445 } else {
446 ++replay_it;
358 }
447 }
359
360 waitingInsts.erase(waiting_it--);
361 }
362 }
363
448 }
449 }
450
364 if (!readyInsts.empty()) {
365 sn_it_t ready_it = readyInsts.end();
451 ListIt squash_it = instList[tid].end();
452 --squash_it;
366
453
367 --ready_it;
454 MemDepHashIt hash_it;
368
455
369 // Same for the ready list.
370 while (!readyInsts.empty() &&
371 (*ready_it) > squashed_num)
372 {
373 readyInsts.erase(ready_it--);
374 }
375 }
456 while (!instList[tid].empty() &&
457 (*squash_it)->seqNum > squashed_num) {
376
458
377 if (!storeDependents.empty()) {
378 sd_it_t dep_it = storeDependents.end();
459 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
460 (*squash_it)->seqNum);
379
461
380 --dep_it;
462 hash_it = memDepHash.find((*squash_it)->seqNum);
381
463
382 // Same for the dependencies list.
383 while (!storeDependents.empty() &&
384 (*dep_it).first > squashed_num)
385 {
386 // This store's list of dependent instructions should be empty.
387 assert((*dep_it).second.empty());
464 assert(hash_it != memDepHash.end());
388
465
389 storeDependents.erase(dep_it--);
390 }
466 (*hash_it).second->squashed = true;
467
468 (*hash_it).second = NULL;
469
470 memDepHash.erase(hash_it);
471 MemDepEntry::memdep_erase++;
472
473 instList[tid].erase(squash_it--);
391 }
392
393 // Tell the dependency predictor to squash as well.
474 }
475
476 // Tell the dependency predictor to squash as well.
394 depPred.squash(squashed_num);
477 depPred.squash(squashed_num, tid);
395}
396
397template <class MemDepPred, class Impl>
398void
399MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
400 DynInstPtr &violating_load)
401{
478}
479
480template <class MemDepPred, class Impl>
481void
482MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
483 DynInstPtr &violating_load)
484{
402 DPRINTF(MemDepUnit, "MemDepUnit: Passing violating PCs to store sets,"
485 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
403 " load: %#x, store: %#x\n", violating_load->readPC(),
404 store_inst->readPC());
405 // Tell the memory dependence unit of the violation.
406 depPred.violation(violating_load->readPC(), store_inst->readPC());
407}
408
409template <class MemDepPred, class Impl>
486 " load: %#x, store: %#x\n", violating_load->readPC(),
487 store_inst->readPC());
488 // Tell the memory dependence unit of the violation.
489 depPred.violation(violating_load->readPC(), store_inst->readPC());
490}
491
492template <class MemDepPred, class Impl>
493void
494MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
495{
496 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
497 inst->readPC(), inst->seqNum);
498
499 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
500}
501
502template <class MemDepPred, class Impl>
503inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
504MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
505{
506 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
507
508 assert(hash_it != memDepHash.end());
509
510 return (*hash_it).second;
511}
512
513template <class MemDepPred, class Impl>
410inline void
514inline void
411MemDepUnit<MemDepPred, Impl>::moveToReady(dep_it_t &woken_inst)
515MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
412{
516{
413 DPRINTF(MemDepUnit, "MemDepUnit: Adding instruction sequence number %i "
414 "to the ready list.\n", (*woken_inst).seqNum);
517 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
518 "to the ready list.\n", woken_inst_entry->inst->seqNum);
415
519
416 // Add it to the ready list.
417 readyInsts.insert((*woken_inst).seqNum);
520 assert(!woken_inst_entry->squashed);
418
521
419 // Remove it from the waiting instructions.
420 waitingInsts.erase(woken_inst);
522 iqPtr->addReadyMemInst(woken_inst_entry->inst);
421}
523}
524
525
526template <class MemDepPred, class Impl>
527void
528MemDepUnit<MemDepPred, Impl>::dumpLists()
529{
530 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
531 cprintf("Instruction list %i size: %i\n",
532 tid, instList[tid].size());
533
534 ListIt inst_list_it = instList[tid].begin();
535 int num = 0;
536
537 while (inst_list_it != instList[tid].end()) {
538 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
539 "Squashed:%i\n\n",
540 num, (*inst_list_it)->readPC(),
541 (*inst_list_it)->seqNum,
542 (*inst_list_it)->threadNumber,
543 (*inst_list_it)->isIssued(),
544 (*inst_list_it)->isSquashed());
545 inst_list_it++;
546 ++num;
547 }
548 }
549
550 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
551
552 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
553}