mem_dep_unit_impl.hh (2654:9559cfa91b9d) mem_dep_unit_impl.hh (2665:a124942bacb8)
1/*
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

--- 8 unchanged lines hidden (view full) ---

19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
27 */
28
29#include <map>
30
29 */
30
31#include <map>
32
31#include "cpu/o3/inst_queue.hh"
32#include "cpu/o3/mem_dep_unit.hh"
33
34template <class MemDepPred, class Impl>
33#include "cpu/o3/mem_dep_unit.hh"
34
35template <class MemDepPred, class Impl>
35MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
36 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
37 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
36MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)
37 : depPred(params.SSITSize, params.LFSTSize)
38{
38{
39 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
39 DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n");
40}
41
42template <class MemDepPred, class Impl>
40}
41
42template <class MemDepPred, class Impl>
43MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
44{
45 for (int tid=0; tid < Impl::MaxThreads; tid++) {
46
47 ListIt inst_list_it = instList[tid].begin();
48
49 MemDepHashIt hash_it;
50
51 while (!instList[tid].empty()) {
52 hash_it = memDepHash.find((*inst_list_it)->seqNum);
53
54 assert(hash_it != memDepHash.end());
55
56 memDepHash.erase(hash_it);
57
58 instList[tid].erase(inst_list_it++);
59 }
60 }
61
62 assert(MemDepEntry::memdep_count == 0);
63}
64
65template <class MemDepPred, class Impl>
66std::string
67MemDepUnit<MemDepPred, Impl>::name() const
68{
69 return "memdepunit";
70}
71
72template <class MemDepPred, class Impl>
73void
43void
74MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
75{
76 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
77
78 id = tid;
79
80 depPred.init(params->SSITSize, params->LFSTSize);
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::regStats()
86{
87 insertedLoads
88 .name(name() + ".memDep.insertedLoads")
89 .desc("Number of loads inserted to the mem dependence unit.");
90
91 insertedStores
92 .name(name() + ".memDep.insertedStores")

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98
99 conflictingStores
100 .name(name() + ".memDep.conflictingStores")
101 .desc("Number of conflicting stores.");
102}
103
104template <class MemDepPred, class Impl>
105void
44MemDepUnit<MemDepPred, Impl>::regStats()
45{
46 insertedLoads
47 .name(name() + ".memDep.insertedLoads")
48 .desc("Number of loads inserted to the mem dependence unit.");
49
50 insertedStores
51 .name(name() + ".memDep.insertedStores")

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57
58 conflictingStores
59 .name(name() + ".memDep.conflictingStores")
60 .desc("Number of conflicting stores.");
61}
62
63template <class MemDepPred, class Impl>
64void
106MemDepUnit<MemDepPred, Impl>::switchOut()
107{
108 for (int i = 0; i < Impl::MaxThreads; ++i) {
109 instList[i].clear();
110 }
111 instsToReplay.clear();
112 memDepHash.clear();
113}
114
115template <class MemDepPred, class Impl>
116void
117MemDepUnit<MemDepPred, Impl>::takeOverFrom()
118{
119 loadBarrier = storeBarrier = false;
120 loadBarrierSN = storeBarrierSN = 0;
121 depPred.clear();
122}
123
124template <class MemDepPred, class Impl>
125void
126MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
127{
128 iqPtr = iq_ptr;
129}
130
131template <class MemDepPred, class Impl>
132void
133MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
134{
65MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
66{
135 unsigned tid = inst->threadNumber;
67 InstSeqNum inst_seq_num = inst->seqNum;
136
68
137 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
69 Dependency unresolved_dependencies(inst_seq_num);
138
70
139 // Add the MemDepEntry to the hash.
140 memDepHash.insert(
141 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
142 MemDepEntry::memdep_insert++;
71 InstSeqNum producing_store = depPred.checkInst(inst->readPC());
143
72
144 instList[tid].push_back(inst);
73 if (producing_store == 0 ||
74 storeDependents.find(producing_store) == storeDependents.end()) {
145
75
146 inst_entry->listIt = --(instList[tid].end());
76 DPRINTF(MemDepUnit, "MemDepUnit: No dependency for inst PC "
77 "%#x.\n", inst->readPC());
147
78
148 // Check any barriers and the dependence predictor for any
149 // producing stores.
150 InstSeqNum producing_store;
151 if (inst->isLoad() && loadBarrier) {
152 producing_store = loadBarrierSN;
153 } else if (inst->isStore() && storeBarrier) {
154 producing_store = storeBarrierSN;
155 } else {
156 producing_store = depPred.checkInst(inst->readPC());
157 }
79 unresolved_dependencies.storeDep = storeDependents.end();
158
80
159 MemDepEntryPtr store_entry = NULL;
160
161 // If there is a producing store, try to find the entry.
162 if (producing_store != 0) {
163 MemDepHashIt hash_it = memDepHash.find(producing_store);
164
165 if (hash_it != memDepHash.end()) {
166 store_entry = (*hash_it).second;
167 }
168 }
169
170 // If no store entry, then instruction can issue as soon as the registers
171 // are ready.
172 if (!store_entry) {
173 DPRINTF(MemDepUnit, "No dependency for inst PC "
174 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
175
176 inst_entry->memDepReady = true;
177
178 if (inst->readyToIssue()) {
81 if (inst->readyToIssue()) {
179 inst_entry->regsReady = true;
82 readyInsts.insert(inst_seq_num);
83 } else {
84 unresolved_dependencies.memDepReady = true;
180
85
181 moveToReady(inst_entry);
86 waitingInsts.insert(unresolved_dependencies);
182 }
183 } else {
87 }
88 } else {
184 // Otherwise make the instruction dependent on the store/barrier.
185 DPRINTF(MemDepUnit, "Adding to dependency list; "
186 "inst PC %#x is dependent on [sn:%lli].\n",
89 DPRINTF(MemDepUnit, "MemDepUnit: Adding to dependency list; "
90 "inst PC %#x is dependent on seq num %i.\n",
187 inst->readPC(), producing_store);
188
189 if (inst->readyToIssue()) {
91 inst->readPC(), producing_store);
92
93 if (inst->readyToIssue()) {
190 inst_entry->regsReady = true;
94 unresolved_dependencies.regsReady = true;
191 }
192
95 }
96
97 // Find the store that this instruction is dependent on.
98 sd_it_t store_loc = storeDependents.find(producing_store);
99
100 assert(store_loc != storeDependents.end());
101
102 // Record the location of the store that this instruction is
103 // dependent on.
104 unresolved_dependencies.storeDep = store_loc;
105
106 // If it's not already ready, then add it to the renamed
107 // list and the dependencies.
108 dep_it_t inst_loc =
109 (waitingInsts.insert(unresolved_dependencies)).first;
110
193 // Add this instruction to the list of dependents.
111 // Add this instruction to the list of dependents.
194 store_entry->dependInsts.push_back(inst_entry);
112 (*store_loc).second.push_back(inst_loc);
195
113
114 assert(!(*store_loc).second.empty());
115
196 if (inst->isLoad()) {
197 ++conflictingLoads;
198 } else {
199 ++conflictingStores;
200 }
201 }
202
203 if (inst->isStore()) {
116 if (inst->isLoad()) {
117 ++conflictingLoads;
118 } else {
119 ++conflictingStores;
120 }
121 }
122
123 if (inst->isStore()) {
204 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
205 inst->readPC(), inst->seqNum);
124 DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
125 inst->readPC());
206
126
207 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
127 depPred.insertStore(inst->readPC(), inst_seq_num);
208
128
129 // Make sure this store isn't already in this list.
130 assert(storeDependents.find(inst_seq_num) == storeDependents.end());
131
132 // Put a dependency entry in at the store's sequence number.
133 // Uh, not sure how this works...I want to create an entry but
134 // I don't have anything to put into the value yet.
135 storeDependents[inst_seq_num];
136
137 assert(storeDependents.size() != 0);
138
209 ++insertedStores;
139 ++insertedStores;
140
210 } else if (inst->isLoad()) {
211 ++insertedLoads;
212 } else {
141 } else if (inst->isLoad()) {
142 ++insertedLoads;
143 } else {
213 panic("Unknown type! (most likely a barrier).");
144 panic("MemDepUnit: Unknown type! (most likely a barrier).");
214 }
145 }
146
147 memInsts[inst_seq_num] = inst;
215}
216
217template <class MemDepPred, class Impl>
218void
219MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
220{
148}
149
150template <class MemDepPred, class Impl>
151void
152MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
153{
221 unsigned tid = inst->threadNumber;
154 InstSeqNum inst_seq_num = inst->seqNum;
222
155
223 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
156 Dependency non_spec_inst(inst_seq_num);
224
157
225 // Insert the MemDepEntry into the hash.
226 memDepHash.insert(
227 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
228 MemDepEntry::memdep_insert++;
158 non_spec_inst.storeDep = storeDependents.end();
229
159
230 // Add the instruction to the list.
231 instList[tid].push_back(inst);
160 waitingInsts.insert(non_spec_inst);
232
161
233 inst_entry->listIt = --(instList[tid].end());
234
235 // Might want to turn this part into an inline function or something.
236 // It's shared between both insert functions.
237 if (inst->isStore()) {
162 // Might want to turn this part into an inline function or something.
163 // It's shared between both insert functions.
164 if (inst->isStore()) {
238 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
239 inst->readPC(), inst->seqNum);
165 DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
166 inst->readPC());
240
167
241 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
168 depPred.insertStore(inst->readPC(), inst_seq_num);
242
169
170 // Make sure this store isn't already in this list.
171 assert(storeDependents.find(inst_seq_num) == storeDependents.end());
172
173 // Put a dependency entry in at the store's sequence number.
174 // Uh, not sure how this works...I want to create an entry but
175 // I don't have anything to put into the value yet.
176 storeDependents[inst_seq_num];
177
178 assert(storeDependents.size() != 0);
179
243 ++insertedStores;
180 ++insertedStores;
181
244 } else if (inst->isLoad()) {
245 ++insertedLoads;
246 } else {
182 } else if (inst->isLoad()) {
183 ++insertedLoads;
184 } else {
247 panic("Unknown type! (most likely a barrier).");
185 panic("MemDepUnit: Unknown type! (most likely a barrier).");
248 }
186 }
187
188 memInsts[inst_seq_num] = inst;
249}
250
251template <class MemDepPred, class Impl>
189}
190
191template <class MemDepPred, class Impl>
252void
253MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
192typename Impl::DynInstPtr &
193MemDepUnit<MemDepPred, Impl>::top()
254{
194{
255 InstSeqNum barr_sn = barr_inst->seqNum;
256 if (barr_inst->isMemBarrier()) {
257 loadBarrier = true;
258 loadBarrierSN = barr_sn;
259 storeBarrier = true;
260 storeBarrierSN = barr_sn;
261 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
262 } else if (barr_inst->isWriteBarrier()) {
263 storeBarrier = true;
264 storeBarrierSN = barr_sn;
265 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
266 }
195 topInst = memInsts.find( (*readyInsts.begin()) );
267
196
268 unsigned tid = barr_inst->threadNumber;
197 DPRINTF(MemDepUnit, "MemDepUnit: Top instruction is PC %#x.\n",
198 (*topInst).second->readPC());
269
199
270 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
271
272 // Add the MemDepEntry to the hash.
273 memDepHash.insert(
274 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
275 MemDepEntry::memdep_insert++;
276
277 // Add the instruction to the instruction list.
278 instList[tid].push_back(barr_inst);
279
280 inst_entry->listIt = --(instList[tid].end());
200 return (*topInst).second;
281}
282
283template <class MemDepPred, class Impl>
284void
201}
202
203template <class MemDepPred, class Impl>
204void
285MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
205MemDepUnit<MemDepPred, Impl>::pop()
286{
206{
287 DPRINTF(MemDepUnit, "Marking registers as ready for "
288 "instruction PC %#x [sn:%lli].\n",
289 inst->readPC(), inst->seqNum);
207 DPRINTF(MemDepUnit, "MemDepUnit: Removing instruction PC %#x.\n",
208 (*topInst).second->readPC());
290
209
291 MemDepEntryPtr inst_entry = findInHash(inst);
210 wakeDependents((*topInst).second);
292
211
293 inst_entry->regsReady = true;
212 issue((*topInst).second);
294
213
295 if (inst_entry->memDepReady) {
296 DPRINTF(MemDepUnit, "Instruction has its memory "
297 "dependencies resolved, adding it to the ready list.\n");
214 memInsts.erase(topInst);
298
215
299 moveToReady(inst_entry);
300 } else {
301 DPRINTF(MemDepUnit, "Instruction still waiting on "
302 "memory dependency.\n");
303 }
216 topInst = memInsts.end();
304}
305
306template <class MemDepPred, class Impl>
307void
217}
218
219template <class MemDepPred, class Impl>
220void
308MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
221MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
309{
222{
310 DPRINTF(MemDepUnit, "Marking non speculative "
311 "instruction PC %#x as ready [sn:%lli].\n",
312 inst->readPC(), inst->seqNum);
223 DPRINTF(MemDepUnit, "MemDepUnit: Marking registers as ready for "
224 "instruction PC %#x.\n",
225 inst->readPC());
313
226
314 MemDepEntryPtr inst_entry = findInHash(inst);
227 InstSeqNum inst_seq_num = inst->seqNum;
315
228
316 moveToReady(inst_entry);
317}
229 Dependency inst_to_find(inst_seq_num);
318
230
319template <class MemDepPred, class Impl>
320void
321MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
322{
323 instsToReplay.push_back(inst);
324}
231 dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
325
232
326template <class MemDepPred, class Impl>
327void
328MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
329{
330 DynInstPtr temp_inst;
331 bool found_inst = false;
233 assert(waiting_inst != waitingInsts.end());
332
234
333 while (!instsToReplay.empty()) {
334 temp_inst = instsToReplay.front();
235 if ((*waiting_inst).memDepReady) {
236 DPRINTF(MemDepUnit, "MemDepUnit: Instruction has its memory "
237 "dependencies resolved, adding it to the ready list.\n");
335
238
336 MemDepEntryPtr inst_entry = findInHash(temp_inst);
239 moveToReady(waiting_inst);
240 } else {
241 DPRINTF(MemDepUnit, "MemDepUnit: Instruction still waiting on "
242 "memory dependency.\n");
337
243
338 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
339 "[sn:%lli].\n",
340 temp_inst->readPC(), temp_inst->seqNum);
341
342 moveToReady(inst_entry);
343
344 if (temp_inst == inst) {
345 found_inst = true;
346 }
347
348 instsToReplay.pop_front();
244 (*waiting_inst).regsReady = true;
349 }
245 }
350
351 assert(found_inst);
352}
353
354template <class MemDepPred, class Impl>
355void
246}
247
248template <class MemDepPred, class Impl>
249void
356MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
250MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
357{
251{
358 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
359 "[sn:%lli].\n",
360 inst->readPC(), inst->seqNum);
252 DPRINTF(MemDepUnit, "MemDepUnit: Marking non speculative "
253 "instruction PC %#x as ready.\n",
254 inst->readPC());
361
255
362 unsigned tid = inst->threadNumber;
256 InstSeqNum inst_seq_num = inst->seqNum;
363
257
364 // Remove the instruction from the hash and the list.
365 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
258 Dependency inst_to_find(inst_seq_num);
366
259
367 assert(hash_it != memDepHash.end());
260 dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
368
261
369 instList[tid].erase((*hash_it).second->listIt);
262 assert(waiting_inst != waitingInsts.end());
370
263
371 (*hash_it).second = NULL;
372
373 memDepHash.erase(hash_it);
374 MemDepEntry::memdep_erase++;
264 moveToReady(waiting_inst);
375}
376
377template <class MemDepPred, class Impl>
378void
265}
266
267template <class MemDepPred, class Impl>
268void
379MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
269MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
380{
270{
381 wakeDependents(inst);
382 completed(inst);
271 assert(readyInsts.find(inst->seqNum) != readyInsts.end());
383
272
384 InstSeqNum barr_sn = inst->seqNum;
273 DPRINTF(MemDepUnit, "MemDepUnit: Issuing instruction PC %#x.\n",
274 inst->readPC());
385
275
386 if (inst->isMemBarrier()) {
387 assert(loadBarrier && storeBarrier);
388 if (loadBarrierSN == barr_sn)
389 loadBarrier = false;
390 if (storeBarrierSN == barr_sn)
391 storeBarrier = false;
392 } else if (inst->isWriteBarrier()) {
393 assert(storeBarrier);
394 if (storeBarrierSN == barr_sn)
395 storeBarrier = false;
396 }
276 // Remove the instruction from the ready list.
277 readyInsts.erase(inst->seqNum);
278
279 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
397}
398
399template <class MemDepPred, class Impl>
400void
401MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
402{
280}
281
282template <class MemDepPred, class Impl>
283void
284MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
285{
403 // Only stores and barriers have dependents.
404 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
286 // Only stores have dependents.
287 if (!inst->isStore()) {
405 return;
406 }
407
288 return;
289 }
290
408 MemDepEntryPtr inst_entry = findInHash(inst);
291 // Wake any dependencies.
292 sd_it_t sd_it = storeDependents.find(inst->seqNum);
409
293
410 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
411 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
294 // If there's no entry, then return. Really there should only be
295 // no entry if the instruction is a load.
296 if (sd_it == storeDependents.end()) {
297 DPRINTF(MemDepUnit, "MemDepUnit: Instruction PC %#x, sequence "
298 "number %i has no dependents.\n",
299 inst->readPC(), inst->seqNum);
412
300
413 if (!woken_inst->inst) {
414 // Potentially removed mem dep entries could be on this list
415 continue;
416 }
301 return;
302 }
417
303
418 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
419 "[sn:%lli].\n",
420 woken_inst->inst->seqNum);
304 for (int i = 0; i < (*sd_it).second.size(); ++i ) {
305 dep_it_t woken_inst = (*sd_it).second[i];
421
306
422 if (woken_inst->regsReady && !woken_inst->squashed) {
307 DPRINTF(MemDepUnit, "MemDepUnit: Waking up a dependent inst, "
308 "sequence number %i.\n",
309 (*woken_inst).seqNum);
310#if 0
311 // Should we have reached instructions that are actually squashed,
312 // there will be no more useful instructions in this dependency
313 // list. Break out early.
314 if (waitingInsts.find(woken_inst) == waitingInsts.end()) {
315 DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x "
316 "are squashed, starting at SN %i. Breaking early.\n",
317 inst->readPC(), woken_inst);
318 break;
319 }
320#endif
321
322 if ((*woken_inst).regsReady) {
423 moveToReady(woken_inst);
424 } else {
323 moveToReady(woken_inst);
324 } else {
425 woken_inst->memDepReady = true;
325 (*woken_inst).memDepReady = true;
426 }
427 }
428
326 }
327 }
328
429 inst_entry->dependInsts.clear();
329 storeDependents.erase(sd_it);
430}
431
432template <class MemDepPred, class Impl>
433void
330}
331
332template <class MemDepPred, class Impl>
333void
434MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
435 unsigned tid)
334MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num)
436{
335{
437 if (!instsToReplay.empty()) {
438 ListIt replay_it = instsToReplay.begin();
439 while (replay_it != instsToReplay.end()) {
440 if ((*replay_it)->threadNumber == tid &&
441 (*replay_it)->seqNum > squashed_num) {
442 instsToReplay.erase(replay_it++);
443 } else {
444 ++replay_it;
445 }
446 }
447 }
448
336
449 ListIt squash_it = instList[tid].end();
450 --squash_it;
337 if (!waitingInsts.empty()) {
338 dep_it_t waiting_it = waitingInsts.end();
451
339
452 MemDepHashIt hash_it;
340 --waiting_it;
453
341
454 while (!instList[tid].empty() &&
455 (*squash_it)->seqNum > squashed_num) {
342 // Remove entries from the renamed list as long as we haven't reached
343 // the end and the entries continue to be younger than the squashed.
344 while (!waitingInsts.empty() &&
345 (*waiting_it).seqNum > squashed_num)
346 {
347 if (!(*waiting_it).memDepReady &&
348 (*waiting_it).storeDep != storeDependents.end()) {
349 sd_it_t sd_it = (*waiting_it).storeDep;
456
350
457 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
458 (*squash_it)->seqNum);
351 // Make sure the iterator that the store has pointing
352 // back is actually to this instruction.
353 assert((*sd_it).second.back() == waiting_it);
459
354
460 hash_it = memDepHash.find((*squash_it)->seqNum);
355 // Now remove this from the store's list of dependent
356 // instructions.
357 (*sd_it).second.pop_back();
358 }
461
359
462 assert(hash_it != memDepHash.end());
360 waitingInsts.erase(waiting_it--);
361 }
362 }
463
363
464 (*hash_it).second->squashed = true;
364 if (!readyInsts.empty()) {
365 sn_it_t ready_it = readyInsts.end();
465
366
466 (*hash_it).second = NULL;
367 --ready_it;
467
368
468 memDepHash.erase(hash_it);
469 MemDepEntry::memdep_erase++;
369 // Same for the ready list.
370 while (!readyInsts.empty() &&
371 (*ready_it) > squashed_num)
372 {
373 readyInsts.erase(ready_it--);
374 }
375 }
470
376
471 instList[tid].erase(squash_it--);
377 if (!storeDependents.empty()) {
378 sd_it_t dep_it = storeDependents.end();
379
380 --dep_it;
381
382 // Same for the dependencies list.
383 while (!storeDependents.empty() &&
384 (*dep_it).first > squashed_num)
385 {
386 // This store's list of dependent instructions should be empty.
387 assert((*dep_it).second.empty());
388
389 storeDependents.erase(dep_it--);
390 }
472 }
473
474 // Tell the dependency predictor to squash as well.
391 }
392
393 // Tell the dependency predictor to squash as well.
475 depPred.squash(squashed_num, tid);
394 depPred.squash(squashed_num);
476}
477
478template <class MemDepPred, class Impl>
479void
480MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
481 DynInstPtr &violating_load)
482{
395}
396
397template <class MemDepPred, class Impl>
398void
399MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
400 DynInstPtr &violating_load)
401{
483 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
402 DPRINTF(MemDepUnit, "MemDepUnit: Passing violating PCs to store sets,"
484 " load: %#x, store: %#x\n", violating_load->readPC(),
485 store_inst->readPC());
486 // Tell the memory dependence unit of the violation.
487 depPred.violation(violating_load->readPC(), store_inst->readPC());
488}
489
490template <class MemDepPred, class Impl>
403 " load: %#x, store: %#x\n", violating_load->readPC(),
404 store_inst->readPC());
405 // Tell the memory dependence unit of the violation.
406 depPred.violation(violating_load->readPC(), store_inst->readPC());
407}
408
409template <class MemDepPred, class Impl>
491void
492MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
493{
494 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
495 inst->readPC(), inst->seqNum);
496
497 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
498}
499
500template <class MemDepPred, class Impl>
501inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
502MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
503{
504 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
505
506 assert(hash_it != memDepHash.end());
507
508 return (*hash_it).second;
509}
510
511template <class MemDepPred, class Impl>
512inline void
410inline void
513MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
411MemDepUnit<MemDepPred, Impl>::moveToReady(dep_it_t &woken_inst)
514{
412{
515 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
516 "to the ready list.\n", woken_inst_entry->inst->seqNum);
413 DPRINTF(MemDepUnit, "MemDepUnit: Adding instruction sequence number %i "
414 "to the ready list.\n", (*woken_inst).seqNum);
517
415
518 assert(!woken_inst_entry->squashed);
416 // Add it to the ready list.
417 readyInsts.insert((*woken_inst).seqNum);
519
418
520 iqPtr->addReadyMemInst(woken_inst_entry->inst);
419 // Remove it from the waiting instructions.
420 waitingInsts.erase(woken_inst);
521}
421}
522
523
524template <class MemDepPred, class Impl>
525void
526MemDepUnit<MemDepPred, Impl>::dumpLists()
527{
528 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
529 cprintf("Instruction list %i size: %i\n",
530 tid, instList[tid].size());
531
532 ListIt inst_list_it = instList[tid].begin();
533 int num = 0;
534
535 while (inst_list_it != instList[tid].end()) {
536 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
537 "Squashed:%i\n\n",
538 num, (*inst_list_it)->readPC(),
539 (*inst_list_it)->seqNum,
540 (*inst_list_it)->threadNumber,
541 (*inst_list_it)->isIssued(),
542 (*inst_list_it)->isSquashed());
543 inst_list_it++;
544 ++num;
545 }
546 }
547
548 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
549
550 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
551}