mem_dep_unit_impl.hh (2632:1bb2f91485ea) | mem_dep_unit_impl.hh (2654:9559cfa91b9d) |
---|---|
1/* | 1/* |
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan | 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan |
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <map> 30 | 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 12 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <map> 30 |
31#include "cpu/o3/inst_queue.hh" |
|
31#include "cpu/o3/mem_dep_unit.hh" 32 33template <class MemDepPred, class Impl> | 32#include "cpu/o3/mem_dep_unit.hh" 33 34template <class MemDepPred, class Impl> |
34MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params ¶ms) 35 : depPred(params.SSITSize, params.LFSTSize) | 35MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) 36 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 37 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) |
36{ | 38{ |
37 DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n"); | 39 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); |
38} 39 40template <class MemDepPred, class Impl> | 40} 41 42template <class MemDepPred, class Impl> |
43MemDepUnit<MemDepPred, Impl>::~MemDepUnit() 44{ 45 for (int tid=0; tid < Impl::MaxThreads; tid++) { 46 47 ListIt inst_list_it = instList[tid].begin(); 48 49 MemDepHashIt hash_it; 50 51 while (!instList[tid].empty()) { 52 hash_it = memDepHash.find((*inst_list_it)->seqNum); 53 54 assert(hash_it != memDepHash.end()); 55 56 memDepHash.erase(hash_it); 57 58 instList[tid].erase(inst_list_it++); 59 } 60 } 61 62 assert(MemDepEntry::memdep_count == 0); 63} 64 65template <class MemDepPred, class Impl> 66std::string 67MemDepUnit<MemDepPred, Impl>::name() const 68{ 69 return "memdepunit"; 70} 71 72template <class MemDepPred, class Impl> |
|
41void | 73void |
74MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid) 75{ 76 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 77 78 id = tid; 79 80 depPred.init(params->SSITSize, params->LFSTSize); 81} 82 83template <class MemDepPred, class Impl> 84void |
|
42MemDepUnit<MemDepPred, Impl>::regStats() 43{ 44 insertedLoads 45 .name(name() + ".memDep.insertedLoads") 46 .desc("Number of loads inserted to the mem dependence unit."); 47 48 insertedStores 49 .name(name() + ".memDep.insertedStores") --- 5 unchanged lines hidden (view full) --- 55 56 conflictingStores 57 .name(name() + ".memDep.conflictingStores") 58 .desc("Number of conflicting stores."); 59} 60 61template <class MemDepPred, class Impl> 62void | 85MemDepUnit<MemDepPred, Impl>::regStats() 86{ 87 insertedLoads 88 .name(name() + ".memDep.insertedLoads") 89 .desc("Number of loads inserted to the mem dependence unit."); 90 91 insertedStores 92 .name(name() + ".memDep.insertedStores") --- 5 unchanged lines hidden (view full) --- 98 99 conflictingStores 100 .name(name() + ".memDep.conflictingStores") 101 .desc("Number of conflicting stores."); 102} 103 104template <class MemDepPred, class Impl> 105void |
106MemDepUnit<MemDepPred, Impl>::switchOut() 107{ 108 for (int i = 0; i < Impl::MaxThreads; ++i) { 109 instList[i].clear(); 110 } 111 instsToReplay.clear(); 112 memDepHash.clear(); 113} 114 115template <class MemDepPred, class Impl> 116void 117MemDepUnit<MemDepPred, Impl>::takeOverFrom() 118{ 119 loadBarrier = storeBarrier = false; 120 loadBarrierSN = storeBarrierSN = 0; 121 depPred.clear(); 122} 123 124template <class MemDepPred, class Impl> 125void 126MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 127{ 128 iqPtr = iq_ptr; 129} 130 131template <class MemDepPred, class Impl> 132void |
|
63MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 64{ | 133MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 134{ |
65 InstSeqNum inst_seq_num = inst->seqNum; | 135 unsigned tid = inst->threadNumber; |
66 | 136 |
67 Dependency unresolved_dependencies(inst_seq_num); | 137 MemDepEntryPtr inst_entry = new MemDepEntry(inst); |
68 | 138 |
69 InstSeqNum producing_store = depPred.checkInst(inst->readPC()); | 139 // Add the MemDepEntry to the hash. 140 memDepHash.insert( 141 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 142 MemDepEntry::memdep_insert++; |
70 | 143 |
71 if (producing_store == 0 || 72 storeDependents.find(producing_store) == storeDependents.end()) { | 144 instList[tid].push_back(inst); |
73 | 145 |
74 DPRINTF(MemDepUnit, "MemDepUnit: No dependency for inst PC " 75 "%#x.\n", inst->readPC()); | 146 inst_entry->listIt = --(instList[tid].end()); |
76 | 147 |
77 unresolved_dependencies.storeDep = storeDependents.end(); | 148 // Check any barriers and the dependence predictor for any 149 // producing stores. 150 InstSeqNum producing_store; 151 if (inst->isLoad() && loadBarrier) { 152 producing_store = loadBarrierSN; 153 } else if (inst->isStore() && storeBarrier) { 154 producing_store = storeBarrierSN; 155 } else { 156 producing_store = depPred.checkInst(inst->readPC()); 157 } |
78 | 158 |
159 MemDepEntryPtr store_entry = NULL; 160 161 // If there is a producing store, try to find the entry. 162 if (producing_store != 0) { 163 MemDepHashIt hash_it = memDepHash.find(producing_store); 164 165 if (hash_it != memDepHash.end()) { 166 store_entry = (*hash_it).second; 167 } 168 } 169 170 // If no store entry, then instruction can issue as soon as the registers 171 // are ready. 172 if (!store_entry) { 173 DPRINTF(MemDepUnit, "No dependency for inst PC " 174 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 175 176 inst_entry->memDepReady = true; 177 |
|
79 if (inst->readyToIssue()) { | 178 if (inst->readyToIssue()) { |
80 readyInsts.insert(inst_seq_num); 81 } else { 82 unresolved_dependencies.memDepReady = true; | 179 inst_entry->regsReady = true; |
83 | 180 |
84 waitingInsts.insert(unresolved_dependencies); | 181 moveToReady(inst_entry); |
85 } 86 } else { | 182 } 183 } else { |
87 DPRINTF(MemDepUnit, "MemDepUnit: Adding to dependency list; " 88 "inst PC %#x is dependent on seq num %i.\n", | 184 // Otherwise make the instruction dependent on the store/barrier. 185 DPRINTF(MemDepUnit, "Adding to dependency list; " 186 "inst PC %#x is dependent on [sn:%lli].\n", |
89 inst->readPC(), producing_store); 90 91 if (inst->readyToIssue()) { | 187 inst->readPC(), producing_store); 188 189 if (inst->readyToIssue()) { |
92 unresolved_dependencies.regsReady = true; | 190 inst_entry->regsReady = true; |
93 } 94 | 191 } 192 |
95 // Find the store that this instruction is dependent on. 96 sd_it_t store_loc = storeDependents.find(producing_store); 97 98 assert(store_loc != storeDependents.end()); 99 100 // Record the location of the store that this instruction is 101 // dependent on. 102 unresolved_dependencies.storeDep = store_loc; 103 104 // If it's not already ready, then add it to the renamed 105 // list and the dependencies. 106 dep_it_t inst_loc = 107 (waitingInsts.insert(unresolved_dependencies)).first; 108 | |
109 // Add this instruction to the list of dependents. | 193 // Add this instruction to the list of dependents. |
110 (*store_loc).second.push_back(inst_loc); | 194 store_entry->dependInsts.push_back(inst_entry); |
111 | 195 |
112 assert(!(*store_loc).second.empty()); 113 | |
114 if (inst->isLoad()) { 115 ++conflictingLoads; 116 } else { 117 ++conflictingStores; 118 } 119 } 120 121 if (inst->isStore()) { | 196 if (inst->isLoad()) { 197 ++conflictingLoads; 198 } else { 199 ++conflictingStores; 200 } 201 } 202 203 if (inst->isStore()) { |
122 DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n", 123 inst->readPC()); | 204 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 205 inst->readPC(), inst->seqNum); |
124 | 206 |
125 depPred.insertStore(inst->readPC(), inst_seq_num); | 207 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); |
126 | 208 |
127 // Make sure this store isn't already in this list. 128 assert(storeDependents.find(inst_seq_num) == storeDependents.end()); 129 130 // Put a dependency entry in at the store's sequence number. 131 // Uh, not sure how this works...I want to create an entry but 132 // I don't have anything to put into the value yet. 133 storeDependents[inst_seq_num]; 134 135 assert(storeDependents.size() != 0); 136 | |
137 ++insertedStores; | 209 ++insertedStores; |
138 | |
139 } else if (inst->isLoad()) { 140 ++insertedLoads; 141 } else { | 210 } else if (inst->isLoad()) { 211 ++insertedLoads; 212 } else { |
142 panic("MemDepUnit: Unknown type! (most likely a barrier)."); | 213 panic("Unknown type! (most likely a barrier)."); |
143 } | 214 } |
144 145 memInsts[inst_seq_num] = inst; | |
146} 147 148template <class MemDepPred, class Impl> 149void 150MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 151{ | 215} 216 217template <class MemDepPred, class Impl> 218void 219MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 220{ |
152 InstSeqNum inst_seq_num = inst->seqNum; | 221 unsigned tid = inst->threadNumber; |
153 | 222 |
154 Dependency non_spec_inst(inst_seq_num); | 223 MemDepEntryPtr inst_entry = new MemDepEntry(inst); |
155 | 224 |
156 non_spec_inst.storeDep = storeDependents.end(); | 225 // Insert the MemDepEntry into the hash. 226 memDepHash.insert( 227 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 228 MemDepEntry::memdep_insert++; |
157 | 229 |
158 waitingInsts.insert(non_spec_inst); | 230 // Add the instruction to the list. 231 instList[tid].push_back(inst); |
159 | 232 |
233 inst_entry->listIt = --(instList[tid].end()); 234 |
|
160 // Might want to turn this part into an inline function or something. 161 // It's shared between both insert functions. 162 if (inst->isStore()) { | 235 // Might want to turn this part into an inline function or something. 236 // It's shared between both insert functions. 237 if (inst->isStore()) { |
163 DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n", 164 inst->readPC()); | 238 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 239 inst->readPC(), inst->seqNum); |
165 | 240 |
166 depPred.insertStore(inst->readPC(), inst_seq_num); | 241 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); |
167 | 242 |
168 // Make sure this store isn't already in this list. 169 assert(storeDependents.find(inst_seq_num) == storeDependents.end()); 170 171 // Put a dependency entry in at the store's sequence number. 172 // Uh, not sure how this works...I want to create an entry but 173 // I don't have anything to put into the value yet. 174 storeDependents[inst_seq_num]; 175 176 assert(storeDependents.size() != 0); 177 | |
178 ++insertedStores; | 243 ++insertedStores; |
179 | |
180 } else if (inst->isLoad()) { 181 ++insertedLoads; 182 } else { | 244 } else if (inst->isLoad()) { 245 ++insertedLoads; 246 } else { |
183 panic("MemDepUnit: Unknown type! (most likely a barrier)."); | 247 panic("Unknown type! (most likely a barrier)."); |
184 } | 248 } |
185 186 memInsts[inst_seq_num] = inst; | |
187} 188 189template <class MemDepPred, class Impl> | 249} 250 251template <class MemDepPred, class Impl> |
190typename Impl::DynInstPtr & 191MemDepUnit<MemDepPred, Impl>::top() | 252void 253MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) |
192{ | 254{ |
193 topInst = memInsts.find( (*readyInsts.begin()) ); | 255 InstSeqNum barr_sn = barr_inst->seqNum; 256 if (barr_inst->isMemBarrier()) { 257 loadBarrier = true; 258 loadBarrierSN = barr_sn; 259 storeBarrier = true; 260 storeBarrierSN = barr_sn; 261 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 262 } else if (barr_inst->isWriteBarrier()) { 263 storeBarrier = true; 264 storeBarrierSN = barr_sn; 265 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 266 } |
194 | 267 |
195 DPRINTF(MemDepUnit, "MemDepUnit: Top instruction is PC %#x.\n", 196 (*topInst).second->readPC()); | 268 unsigned tid = barr_inst->threadNumber; |
197 | 269 |
198 return (*topInst).second; | 270 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 271 272 // Add the MemDepEntry to the hash. 273 memDepHash.insert( 274 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 275 MemDepEntry::memdep_insert++; 276 277 // Add the instruction to the instruction list. 278 instList[tid].push_back(barr_inst); 279 280 inst_entry->listIt = --(instList[tid].end()); |
199} 200 201template <class MemDepPred, class Impl> 202void | 281} 282 283template <class MemDepPred, class Impl> 284void |
203MemDepUnit<MemDepPred, Impl>::pop() | 285MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) |
204{ | 286{ |
205 DPRINTF(MemDepUnit, "MemDepUnit: Removing instruction PC %#x.\n", 206 (*topInst).second->readPC()); | 287 DPRINTF(MemDepUnit, "Marking registers as ready for " 288 "instruction PC %#x [sn:%lli].\n", 289 inst->readPC(), inst->seqNum); |
207 | 290 |
208 wakeDependents((*topInst).second); | 291 MemDepEntryPtr inst_entry = findInHash(inst); |
209 | 292 |
210 issue((*topInst).second); | 293 inst_entry->regsReady = true; |
211 | 294 |
212 memInsts.erase(topInst); | 295 if (inst_entry->memDepReady) { 296 DPRINTF(MemDepUnit, "Instruction has its memory " 297 "dependencies resolved, adding it to the ready list.\n"); |
213 | 298 |
214 topInst = memInsts.end(); | 299 moveToReady(inst_entry); 300 } else { 301 DPRINTF(MemDepUnit, "Instruction still waiting on " 302 "memory dependency.\n"); 303 } |
215} 216 217template <class MemDepPred, class Impl> 218void | 304} 305 306template <class MemDepPred, class Impl> 307void |
219MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) | 308MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) |
220{ | 309{ |
221 DPRINTF(MemDepUnit, "MemDepUnit: Marking registers as ready for " 222 "instruction PC %#x.\n", 223 inst->readPC()); | 310 DPRINTF(MemDepUnit, "Marking non speculative " 311 "instruction PC %#x as ready [sn:%lli].\n", 312 inst->readPC(), inst->seqNum); |
224 | 313 |
225 InstSeqNum inst_seq_num = inst->seqNum; | 314 MemDepEntryPtr inst_entry = findInHash(inst); |
226 | 315 |
227 Dependency inst_to_find(inst_seq_num); | 316 moveToReady(inst_entry); 317} |
228 | 318 |
229 dep_it_t waiting_inst = waitingInsts.find(inst_to_find); | 319template <class MemDepPred, class Impl> 320void 321MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 322{ 323 instsToReplay.push_back(inst); 324} |
230 | 325 |
231 assert(waiting_inst != waitingInsts.end()); | 326template <class MemDepPred, class Impl> 327void 328MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 329{ 330 DynInstPtr temp_inst; 331 bool found_inst = false; |
232 | 332 |
233 if ((*waiting_inst).memDepReady) { 234 DPRINTF(MemDepUnit, "MemDepUnit: Instruction has its memory " 235 "dependencies resolved, adding it to the ready list.\n"); | 333 while (!instsToReplay.empty()) { 334 temp_inst = instsToReplay.front(); |
236 | 335 |
237 moveToReady(waiting_inst); 238 } else { 239 DPRINTF(MemDepUnit, "MemDepUnit: Instruction still waiting on " 240 "memory dependency.\n"); | 336 MemDepEntryPtr inst_entry = findInHash(temp_inst); |
241 | 337 |
242 (*waiting_inst).regsReady = true; | 338 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 339 "[sn:%lli].\n", 340 temp_inst->readPC(), temp_inst->seqNum); 341 342 moveToReady(inst_entry); 343 344 if (temp_inst == inst) { 345 found_inst = true; 346 } 347 348 instsToReplay.pop_front(); |
243 } | 349 } |
350 351 assert(found_inst); |
|
244} 245 246template <class MemDepPred, class Impl> 247void | 352} 353 354template <class MemDepPred, class Impl> 355void |
248MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) | 356MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) |
249{ | 357{ |
250 DPRINTF(MemDepUnit, "MemDepUnit: Marking non speculative " 251 "instruction PC %#x as ready.\n", 252 inst->readPC()); | 358 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 359 "[sn:%lli].\n", 360 inst->readPC(), inst->seqNum); |
253 | 361 |
254 InstSeqNum inst_seq_num = inst->seqNum; | 362 unsigned tid = inst->threadNumber; |
255 | 363 |
256 Dependency inst_to_find(inst_seq_num); | 364 // Remove the instruction from the hash and the list. 365 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); |
257 | 366 |
258 dep_it_t waiting_inst = waitingInsts.find(inst_to_find); | 367 assert(hash_it != memDepHash.end()); |
259 | 368 |
260 assert(waiting_inst != waitingInsts.end()); | 369 instList[tid].erase((*hash_it).second->listIt); |
261 | 370 |
262 moveToReady(waiting_inst); | 371 (*hash_it).second = NULL; 372 373 memDepHash.erase(hash_it); 374 MemDepEntry::memdep_erase++; |
263} 264 265template <class MemDepPred, class Impl> 266void | 375} 376 377template <class MemDepPred, class Impl> 378void |
267MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) | 379MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) |
268{ | 380{ |
269 assert(readyInsts.find(inst->seqNum) != readyInsts.end()); | 381 wakeDependents(inst); 382 completed(inst); |
270 | 383 |
271 DPRINTF(MemDepUnit, "MemDepUnit: Issuing instruction PC %#x.\n", 272 inst->readPC()); | 384 InstSeqNum barr_sn = inst->seqNum; |
273 | 385 |
274 // Remove the instruction from the ready list. 275 readyInsts.erase(inst->seqNum); 276 277 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); | 386 if (inst->isMemBarrier()) { 387 assert(loadBarrier && storeBarrier); 388 if (loadBarrierSN == barr_sn) 389 loadBarrier = false; 390 if (storeBarrierSN == barr_sn) 391 storeBarrier = false; 392 } else if (inst->isWriteBarrier()) { 393 assert(storeBarrier); 394 if (storeBarrierSN == barr_sn) 395 storeBarrier = false; 396 } |
278} 279 280template <class MemDepPred, class Impl> 281void 282MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 283{ | 397} 398 399template <class MemDepPred, class Impl> 400void 401MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 402{ |
284 // Only stores have dependents. 285 if (!inst->isStore()) { | 403 // Only stores and barriers have dependents. 404 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { |
286 return; 287 } 288 | 405 return; 406 } 407 |
289 // Wake any dependencies. 290 sd_it_t sd_it = storeDependents.find(inst->seqNum); | 408 MemDepEntryPtr inst_entry = findInHash(inst); |
291 | 409 |
292 // If there's no entry, then return. Really there should only be 293 // no entry if the instruction is a load. 294 if (sd_it == storeDependents.end()) { 295 DPRINTF(MemDepUnit, "MemDepUnit: Instruction PC %#x, sequence " 296 "number %i has no dependents.\n", 297 inst->readPC(), inst->seqNum); | 410 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 411 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; |
298 | 412 |
299 return; 300 } 301 302 for (int i = 0; i < (*sd_it).second.size(); ++i ) { 303 dep_it_t woken_inst = (*sd_it).second[i]; 304 305 DPRINTF(MemDepUnit, "MemDepUnit: Waking up a dependent inst, " 306 "sequence number %i.\n", 307 (*woken_inst).seqNum); 308#if 0 309 // Should we have reached instructions that are actually squashed, 310 // there will be no more useful instructions in this dependency 311 // list. Break out early. 312 if (waitingInsts.find(woken_inst) == waitingInsts.end()) { 313 DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x " 314 "are squashed, starting at SN %i. Breaking early.\n", 315 inst->readPC(), woken_inst); 316 break; | 413 if (!woken_inst->inst) { 414 // Potentially removed mem dep entries could be on this list 415 continue; |
317 } | 416 } |
318#endif | |
319 | 417 |
320 if ((*woken_inst).regsReady) { | 418 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 419 "[sn:%lli].\n", 420 woken_inst->inst->seqNum); 421 422 if (woken_inst->regsReady && !woken_inst->squashed) { |
321 moveToReady(woken_inst); 322 } else { | 423 moveToReady(woken_inst); 424 } else { |
323 (*woken_inst).memDepReady = true; | 425 woken_inst->memDepReady = true; |
324 } 325 } 326 | 426 } 427 } 428 |
327 storeDependents.erase(sd_it); | 429 inst_entry->dependInsts.clear(); |
328} 329 330template <class MemDepPred, class Impl> 331void | 430} 431 432template <class MemDepPred, class Impl> 433void |
332MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num) | 434MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 435 unsigned tid) |
333{ | 436{ |
334 335 if (!waitingInsts.empty()) { 336 dep_it_t waiting_it = waitingInsts.end(); 337 338 --waiting_it; 339 340 // Remove entries from the renamed list as long as we haven't reached 341 // the end and the entries continue to be younger than the squashed. 342 while (!waitingInsts.empty() && 343 (*waiting_it).seqNum > squashed_num) 344 { 345 if (!(*waiting_it).memDepReady && 346 (*waiting_it).storeDep != storeDependents.end()) { 347 sd_it_t sd_it = (*waiting_it).storeDep; 348 349 // Make sure the iterator that the store has pointing 350 // back is actually to this instruction. 351 assert((*sd_it).second.back() == waiting_it); 352 353 // Now remove this from the store's list of dependent 354 // instructions. 355 (*sd_it).second.pop_back(); | 437 if (!instsToReplay.empty()) { 438 ListIt replay_it = instsToReplay.begin(); 439 while (replay_it != instsToReplay.end()) { 440 if ((*replay_it)->threadNumber == tid && 441 (*replay_it)->seqNum > squashed_num) { 442 instsToReplay.erase(replay_it++); 443 } else { 444 ++replay_it; |
356 } | 445 } |
357 358 waitingInsts.erase(waiting_it--); | |
359 } 360 } 361 | 446 } 447 } 448 |
362 if (!readyInsts.empty()) { 363 sn_it_t ready_it = readyInsts.end(); | 449 ListIt squash_it = instList[tid].end(); 450 --squash_it; |
364 | 451 |
365 --ready_it; | 452 MemDepHashIt hash_it; |
366 | 453 |
367 // Same for the ready list. 368 while (!readyInsts.empty() && 369 (*ready_it) > squashed_num) 370 { 371 readyInsts.erase(ready_it--); 372 } 373 } | 454 while (!instList[tid].empty() && 455 (*squash_it)->seqNum > squashed_num) { |
374 | 456 |
375 if (!storeDependents.empty()) { 376 sd_it_t dep_it = storeDependents.end(); | 457 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 458 (*squash_it)->seqNum); |
377 | 459 |
378 --dep_it; | 460 hash_it = memDepHash.find((*squash_it)->seqNum); |
379 | 461 |
380 // Same for the dependencies list. 381 while (!storeDependents.empty() && 382 (*dep_it).first > squashed_num) 383 { 384 // This store's list of dependent instructions should be empty. 385 assert((*dep_it).second.empty()); | 462 assert(hash_it != memDepHash.end()); |
386 | 463 |
387 storeDependents.erase(dep_it--); 388 } | 464 (*hash_it).second->squashed = true; 465 466 (*hash_it).second = NULL; 467 468 memDepHash.erase(hash_it); 469 MemDepEntry::memdep_erase++; 470 471 instList[tid].erase(squash_it--); |
389 } 390 391 // Tell the dependency predictor to squash as well. | 472 } 473 474 // Tell the dependency predictor to squash as well. |
392 depPred.squash(squashed_num); | 475 depPred.squash(squashed_num, tid); |
393} 394 395template <class MemDepPred, class Impl> 396void 397MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 398 DynInstPtr &violating_load) 399{ | 476} 477 478template <class MemDepPred, class Impl> 479void 480MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 481 DynInstPtr &violating_load) 482{ |
400 DPRINTF(MemDepUnit, "MemDepUnit: Passing violating PCs to store sets," | 483 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," |
401 " load: %#x, store: %#x\n", violating_load->readPC(), 402 store_inst->readPC()); 403 // Tell the memory dependence unit of the violation. 404 depPred.violation(violating_load->readPC(), store_inst->readPC()); 405} 406 407template <class MemDepPred, class Impl> | 484 " load: %#x, store: %#x\n", violating_load->readPC(), 485 store_inst->readPC()); 486 // Tell the memory dependence unit of the violation. 487 depPred.violation(violating_load->readPC(), store_inst->readPC()); 488} 489 490template <class MemDepPred, class Impl> |
491void 492MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 493{ 494 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 495 inst->readPC(), inst->seqNum); 496 497 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 498} 499 500template <class MemDepPred, class Impl> 501inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 502MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 503{ 504 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 505 506 assert(hash_it != memDepHash.end()); 507 508 return (*hash_it).second; 509} 510 511template <class MemDepPred, class Impl> |
|
408inline void | 512inline void |
409MemDepUnit<MemDepPred, Impl>::moveToReady(dep_it_t &woken_inst) | 513MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) |
410{ | 514{ |
411 DPRINTF(MemDepUnit, "MemDepUnit: Adding instruction sequence number %i " 412 "to the ready list.\n", (*woken_inst).seqNum); | 515 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 516 "to the ready list.\n", woken_inst_entry->inst->seqNum); |
413 | 517 |
414 // Add it to the ready list. 415 readyInsts.insert((*woken_inst).seqNum); | 518 assert(!woken_inst_entry->squashed); |
416 | 519 |
417 // Remove it from the waiting instructions. 418 waitingInsts.erase(woken_inst); | 520 iqPtr->addReadyMemInst(woken_inst_entry->inst); |
419} | 521} |
522 523 524template <class MemDepPred, class Impl> 525void 526MemDepUnit<MemDepPred, Impl>::dumpLists() 527{ 528 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 529 cprintf("Instruction list %i size: %i\n", 530 tid, instList[tid].size()); 531 532 ListIt inst_list_it = instList[tid].begin(); 533 int num = 0; 534 535 while (inst_list_it != instList[tid].end()) { 536 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 537 "Squashed:%i\n\n", 538 num, (*inst_list_it)->readPC(), 539 (*inst_list_it)->seqNum, 540 (*inst_list_it)->threadNumber, 541 (*inst_list_it)->isIssued(), 542 (*inst_list_it)->isSquashed()); 543 inst_list_it++; 544 ++num; 545 } 546 } 547 548 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 549 550 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 551} |
|