mem_dep_unit_impl.hh (10510:7e54a9a9f6b2) mem_dep_unit_impl.hh (13429:a1e199fd8122)
1/*
2 * Copyright (c) 2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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166void
167MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
168{
169 iqPtr = iq_ptr;
170}
171
172template <class MemDepPred, class Impl>
173void
1/*
2 * Copyright (c) 2012, 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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166void
167MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
168{
169 iqPtr = iq_ptr;
170}
171
172template <class MemDepPred, class Impl>
173void
174MemDepUnit::insert(DynInstPtr &inst)
174MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst)
175{
176 ThreadID tid = inst->threadNumber;
177
178 MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
179
180 // Add the MemDepEntry to the hash.
181 memDepHash.insert(
182 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));

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263 ++insertedLoads;
264 } else {
265 panic("Unknown type! (most likely a barrier).");
266 }
267}
268
269template <class MemDepPred, class Impl>
270void
175{
176 ThreadID tid = inst->threadNumber;
177
178 MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
179
180 // Add the MemDepEntry to the hash.
181 memDepHash.insert(
182 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));

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263 ++insertedLoads;
264 } else {
265 panic("Unknown type! (most likely a barrier).");
266 }
267}
268
269template <class MemDepPred, class Impl>
270void
271MemDepUnit::insertNonSpec(DynInstPtr &inst)
271MemDepUnit<MemDepPred, Impl>::insertNonSpec(const DynInstPtr &inst)
272{
273 ThreadID tid = inst->threadNumber;
274
275 MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
276
277 // Insert the MemDepEntry into the hash.
278 memDepHash.insert(
279 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));

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299 ++insertedLoads;
300 } else {
301 panic("Unknown type! (most likely a barrier).");
302 }
303}
304
305template <class MemDepPred, class Impl>
306void
272{
273 ThreadID tid = inst->threadNumber;
274
275 MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
276
277 // Insert the MemDepEntry into the hash.
278 memDepHash.insert(
279 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));

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299 ++insertedLoads;
300 } else {
301 panic("Unknown type! (most likely a barrier).");
302 }
303}
304
305template <class MemDepPred, class Impl>
306void
307MemDepUnit::insertBarrier(DynInstPtr &barr_inst)
307MemDepUnit<MemDepPred, Impl>::insertBarrier(const DynInstPtr &barr_inst)
308{
309 InstSeqNum barr_sn = barr_inst->seqNum;
310 // Memory barriers block loads and stores, write barriers only stores.
311 if (barr_inst->isMemBarrier()) {
312 loadBarrier = true;
313 loadBarrierSN = barr_sn;
314 storeBarrier = true;
315 storeBarrierSN = barr_sn;

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335 // Add the instruction to the instruction list.
336 instList[tid].push_back(barr_inst);
337
338 inst_entry->listIt = --(instList[tid].end());
339}
340
341template <class MemDepPred, class Impl>
342void
308{
309 InstSeqNum barr_sn = barr_inst->seqNum;
310 // Memory barriers block loads and stores, write barriers only stores.
311 if (barr_inst->isMemBarrier()) {
312 loadBarrier = true;
313 loadBarrierSN = barr_sn;
314 storeBarrier = true;
315 storeBarrierSN = barr_sn;

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335 // Add the instruction to the instruction list.
336 instList[tid].push_back(barr_inst);
337
338 inst_entry->listIt = --(instList[tid].end());
339}
340
341template <class MemDepPred, class Impl>
342void
343MemDepUnit::regsReady(DynInstPtr &inst)
343MemDepUnit<MemDepPred, Impl>::regsReady(const DynInstPtr &inst)
344{
345 DPRINTF(MemDepUnit, "Marking registers as ready for "
346 "instruction PC %s [sn:%lli].\n",
347 inst->pcState(), inst->seqNum);
348
349 MemDepEntryPtr inst_entry = findInHash(inst);
350
351 inst_entry->regsReady = true;

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358 } else {
359 DPRINTF(MemDepUnit, "Instruction still waiting on "
360 "memory dependency.\n");
361 }
362}
363
364template <class MemDepPred, class Impl>
365void
344{
345 DPRINTF(MemDepUnit, "Marking registers as ready for "
346 "instruction PC %s [sn:%lli].\n",
347 inst->pcState(), inst->seqNum);
348
349 MemDepEntryPtr inst_entry = findInHash(inst);
350
351 inst_entry->regsReady = true;

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358 } else {
359 DPRINTF(MemDepUnit, "Instruction still waiting on "
360 "memory dependency.\n");
361 }
362}
363
364template <class MemDepPred, class Impl>
365void
366MemDepUnit::nonSpecInstReady(DynInstPtr &inst)
366MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(const DynInstPtr &inst)
367{
368 DPRINTF(MemDepUnit, "Marking non speculative "
369 "instruction PC %s as ready [sn:%lli].\n",
370 inst->pcState(), inst->seqNum);
371
372 MemDepEntryPtr inst_entry = findInHash(inst);
373
374 moveToReady(inst_entry);
375}
376
377template <class MemDepPred, class Impl>
378void
367{
368 DPRINTF(MemDepUnit, "Marking non speculative "
369 "instruction PC %s as ready [sn:%lli].\n",
370 inst->pcState(), inst->seqNum);
371
372 MemDepEntryPtr inst_entry = findInHash(inst);
373
374 moveToReady(inst_entry);
375}
376
377template <class MemDepPred, class Impl>
378void
379MemDepUnit::reschedule(DynInstPtr &inst)
379MemDepUnit<MemDepPred, Impl>::reschedule(const DynInstPtr &inst)
380{
381 instsToReplay.push_back(inst);
382}
383
384template <class MemDepPred, class Impl>
385void
386MemDepUnit<MemDepPred, Impl>::replay()
387{

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399 moveToReady(inst_entry);
400
401 instsToReplay.pop_front();
402 }
403}
404
405template <class MemDepPred, class Impl>
406void
380{
381 instsToReplay.push_back(inst);
382}
383
384template <class MemDepPred, class Impl>
385void
386MemDepUnit<MemDepPred, Impl>::replay()
387{

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399 moveToReady(inst_entry);
400
401 instsToReplay.pop_front();
402 }
403}
404
405template <class MemDepPred, class Impl>
406void
407MemDepUnit::completed(DynInstPtr &inst)
407MemDepUnit<MemDepPred, Impl>::completed(const DynInstPtr &inst)
408{
409 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
410 inst->pcState(), inst->seqNum);
411
412 ThreadID tid = inst->threadNumber;
413
414 // Remove the instruction from the hash and the list.
415 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);

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423 memDepHash.erase(hash_it);
424#ifdef DEBUG
425 MemDepEntry::memdep_erase++;
426#endif
427}
428
429template <class MemDepPred, class Impl>
430void
408{
409 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
410 inst->pcState(), inst->seqNum);
411
412 ThreadID tid = inst->threadNumber;
413
414 // Remove the instruction from the hash and the list.
415 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);

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423 memDepHash.erase(hash_it);
424#ifdef DEBUG
425 MemDepEntry::memdep_erase++;
426#endif
427}
428
429template <class MemDepPred, class Impl>
430void
431MemDepUnit::completeBarrier(DynInstPtr &inst)
431MemDepUnit<MemDepPred, Impl>::completeBarrier(const DynInstPtr &inst)
432{
433 wakeDependents(inst);
434 completed(inst);
435
436 InstSeqNum barr_sn = inst->seqNum;
437 DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
438 inst->seqNum);
439 if (inst->isMemBarrier()) {

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444 } else if (inst->isWriteBarrier()) {
445 if (storeBarrierSN == barr_sn)
446 storeBarrier = false;
447 }
448}
449
450template <class MemDepPred, class Impl>
451void
432{
433 wakeDependents(inst);
434 completed(inst);
435
436 InstSeqNum barr_sn = inst->seqNum;
437 DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
438 inst->seqNum);
439 if (inst->isMemBarrier()) {

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444 } else if (inst->isWriteBarrier()) {
445 if (storeBarrierSN == barr_sn)
446 storeBarrier = false;
447 }
448}
449
450template <class MemDepPred, class Impl>
451void
452MemDepUnit::wakeDependents(DynInstPtr &inst)
452MemDepUnit<MemDepPred, Impl>::wakeDependents(const DynInstPtr &inst)
453{
454 // Only stores and barriers have dependents.
455 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
456 return;
457 }
458
459 MemDepEntryPtr inst_entry = findInHash(inst);
460

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531 }
532
533 // Tell the dependency predictor to squash as well.
534 depPred.squash(squashed_num, tid);
535}
536
537template <class MemDepPred, class Impl>
538void
453{
454 // Only stores and barriers have dependents.
455 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
456 return;
457 }
458
459 MemDepEntryPtr inst_entry = findInHash(inst);
460

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531 }
532
533 // Tell the dependency predictor to squash as well.
534 depPred.squash(squashed_num, tid);
535}
536
537template <class MemDepPred, class Impl>
538void
539MemDepUnit::violation(DynInstPtr &store_inst,
540 DynInstPtr &violating_load)
539MemDepUnit<MemDepPred, Impl>::violation(const DynInstPtr &store_inst,
540 const DynInstPtr &violating_load)
541{
542 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
543 " load: %#x, store: %#x\n", violating_load->instAddr(),
544 store_inst->instAddr());
545 // Tell the memory dependence unit of the violation.
546 depPred.violation(store_inst->instAddr(), violating_load->instAddr());
547}
548
549template <class MemDepPred, class Impl>
550void
541{
542 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
543 " load: %#x, store: %#x\n", violating_load->instAddr(),
544 store_inst->instAddr());
545 // Tell the memory dependence unit of the violation.
546 depPred.violation(store_inst->instAddr(), violating_load->instAddr());
547}
548
549template <class MemDepPred, class Impl>
550void
551MemDepUnit::issue(DynInstPtr &inst)
551MemDepUnit<MemDepPred, Impl>::issue(const DynInstPtr &inst)
552{
553 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
554 inst->instAddr(), inst->seqNum);
555
556 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
557}
558
559template <class MemDepPred, class Impl>
560inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
552{
553 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
554 inst->instAddr(), inst->seqNum);
555
556 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
557}
558
559template <class MemDepPred, class Impl>
560inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
561MemDepUnit::findInHash(const DynInstPtr &inst)
561MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstConstPtr &inst)
562{
563 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
564
565 assert(hash_it != memDepHash.end());
566
567 return (*hash_it).second;
568}
569

--- 45 unchanged lines hidden --- 		562{
563 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
564
565 assert(hash_it != memDepHash.end());
566
567 return (*hash_it).second;
568}
569

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