1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 .name(name() + ".memDep.conflictingStores") 103 .desc("Number of conflicting stores."); 104} 105 106template <class MemDepPred, class Impl> 107void 108MemDepUnit<MemDepPred, Impl>::switchOut() 109{ |
110 // Clear any state. |
111 for (int i = 0; i < Impl::MaxThreads; ++i) { 112 instList[i].clear(); 113 } 114 instsToReplay.clear(); 115 memDepHash.clear(); 116} 117 118template <class MemDepPred, class Impl> 119void 120MemDepUnit<MemDepPred, Impl>::takeOverFrom() 121{ |
122 // Be sure to reset all state. |
123 loadBarrier = storeBarrier = false; 124 loadBarrierSN = storeBarrierSN = 0; 125 depPred.clear(); 126} 127 128template <class MemDepPred, class Impl> 129void 130MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) --- 14 unchanged lines hidden (view full) --- 145 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 146 MemDepEntry::memdep_insert++; 147 148 instList[tid].push_back(inst); 149 150 inst_entry->listIt = --(instList[tid].end()); 151 152 // Check any barriers and the dependence predictor for any |
153 // producing memrefs/stores. |
154 InstSeqNum producing_store; 155 if (inst->isLoad() && loadBarrier) { 156 producing_store = loadBarrierSN; 157 } else if (inst->isStore() && storeBarrier) { 158 producing_store = storeBarrierSN; 159 } else { 160 producing_store = depPred.checkInst(inst->readPC()); 161 } --- 90 unchanged lines hidden (view full) --- 252 } 253} 254 255template <class MemDepPred, class Impl> 256void 257MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 258{ 259 InstSeqNum barr_sn = barr_inst->seqNum; |
260 // Memory barriers block loads and stores, write barriers only stores. |
261 if (barr_inst->isMemBarrier()) { 262 loadBarrier = true; 263 loadBarrierSN = barr_sn; 264 storeBarrier = true; 265 storeBarrierSN = barr_sn; 266 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 267 } else if (barr_inst->isWriteBarrier()) { 268 storeBarrier = true; --- 61 unchanged lines hidden (view full) --- 330 331template <class MemDepPred, class Impl> 332void 333MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 334{ 335 DynInstPtr temp_inst; 336 bool found_inst = false; 337 |
338 // For now this replay function replays all waiting memory ops. |
339 while (!instsToReplay.empty()) { 340 temp_inst = instsToReplay.front(); 341 342 MemDepEntryPtr inst_entry = findInHash(temp_inst); 343 344 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 345 "[sn:%lli].\n", 346 temp_inst->readPC(), temp_inst->seqNum); --- 211 unchanged lines hidden --- |