mem_dep_unit_impl.hh (8232:b28d06a175be) mem_dep_unit_impl.hh (8515:12420b96b364)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35#include "debug/MemDepUnit.hh"
36#include "params/DerivO3CPU.hh"
37
38template <class MemDepPred, class Impl>
39MemDepUnit<MemDepPred, Impl>::MemDepUnit()
40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
41 storeBarrierSN(0), iqPtr(NULL)
42{
43}
44
45template <class MemDepPred, class Impl>
46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
47 : _name(params->name + ".memdepunit"),
48 depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
49 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
50{
51 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
52}
53
54template <class MemDepPred, class Impl>
55MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
56{
57 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
58
59 ListIt inst_list_it = instList[tid].begin();
60
61 MemDepHashIt hash_it;
62
63 while (!instList[tid].empty()) {
64 hash_it = memDepHash.find((*inst_list_it)->seqNum);
65
66 assert(hash_it != memDepHash.end());
67
68 memDepHash.erase(hash_it);
69
70 instList[tid].erase(inst_list_it++);
71 }
72 }
73
74#ifdef DEBUG
75 assert(MemDepEntry::memdep_count == 0);
76#endif
77}
78
79template <class MemDepPred, class Impl>
80void
81MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
82{
83 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
84
85 _name = csprintf("%s.memDep%d", params->name, tid);
86 id = tid;
87
88 depPred.init(params->SSITSize, params->LFSTSize);
89}
90
91template <class MemDepPred, class Impl>
92void
93MemDepUnit<MemDepPred, Impl>::regStats()
94{
95 insertedLoads
96 .name(name() + ".insertedLoads")
97 .desc("Number of loads inserted to the mem dependence unit.");
98
99 insertedStores
100 .name(name() + ".insertedStores")
101 .desc("Number of stores inserted to the mem dependence unit.");
102
103 conflictingLoads
104 .name(name() + ".conflictingLoads")
105 .desc("Number of conflicting loads.");
106
107 conflictingStores
108 .name(name() + ".conflictingStores")
109 .desc("Number of conflicting stores.");
110}
111
112template <class MemDepPred, class Impl>
113void
114MemDepUnit<MemDepPred, Impl>::switchOut()
115{
116 assert(instList[0].empty());
117 assert(instsToReplay.empty());
118 assert(memDepHash.empty());
119 // Clear any state.
120 for (int i = 0; i < Impl::MaxThreads; ++i) {
121 instList[i].clear();
122 }
123 instsToReplay.clear();
124 memDepHash.clear();
125}
126
127template <class MemDepPred, class Impl>
128void
129MemDepUnit<MemDepPred, Impl>::takeOverFrom()
130{
131 // Be sure to reset all state.
132 loadBarrier = storeBarrier = false;
133 loadBarrierSN = storeBarrierSN = 0;
134 depPred.clear();
135}
136
137template <class MemDepPred, class Impl>
138void
139MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
140{
141 iqPtr = iq_ptr;
142}
143
144template <class MemDepPred, class Impl>
145void
146MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
147{
148 ThreadID tid = inst->threadNumber;
149
150 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
151
152 // Add the MemDepEntry to the hash.
153 memDepHash.insert(
154 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
155#ifdef DEBUG
156 MemDepEntry::memdep_insert++;
157#endif
158
159 instList[tid].push_back(inst);
160
161 inst_entry->listIt = --(instList[tid].end());
162
163 // Check any barriers and the dependence predictor for any
164 // producing memrefs/stores.
165 InstSeqNum producing_store;
166 if (inst->isLoad() && loadBarrier) {
167 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
168 loadBarrierSN);
169 producing_store = loadBarrierSN;
170 } else if (inst->isStore() && storeBarrier) {
171 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
172 storeBarrierSN);
173 producing_store = storeBarrierSN;
174 } else {
175 producing_store = depPred.checkInst(inst->instAddr());
176 }
177
178 MemDepEntryPtr store_entry = NULL;
179
180 // If there is a producing store, try to find the entry.
181 if (producing_store != 0) {
182 DPRINTF(MemDepUnit, "Searching for producer\n");
183 MemDepHashIt hash_it = memDepHash.find(producing_store);
184
185 if (hash_it != memDepHash.end()) {
186 store_entry = (*hash_it).second;
187 DPRINTF(MemDepUnit, "Proucer found\n");
188 }
189 }
190
191 // If no store entry, then instruction can issue as soon as the registers
192 // are ready.
193 if (!store_entry) {
194 DPRINTF(MemDepUnit, "No dependency for inst PC "
195 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
196
197 inst_entry->memDepReady = true;
198
199 if (inst->readyToIssue()) {
200 inst_entry->regsReady = true;
201
202 moveToReady(inst_entry);
203 }
204 } else {
205 // Otherwise make the instruction dependent on the store/barrier.
206 DPRINTF(MemDepUnit, "Adding to dependency list; "
207 "inst PC %s is dependent on [sn:%lli].\n",
208 inst->pcState(), producing_store);
209
210 if (inst->readyToIssue()) {
211 inst_entry->regsReady = true;
212 }
213
214 // Clear the bit saying this instruction can issue.
215 inst->clearCanIssue();
216
217 // Add this instruction to the list of dependents.
218 store_entry->dependInsts.push_back(inst_entry);
219
220 if (inst->isLoad()) {
221 ++conflictingLoads;
222 } else {
223 ++conflictingStores;
224 }
225 }
226
227 if (inst->isStore()) {
228 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
229 inst->pcState(), inst->seqNum);
230
231 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
232
233 ++insertedStores;
234 } else if (inst->isLoad()) {
235 ++insertedLoads;
236 } else {
237 panic("Unknown type! (most likely a barrier).");
238 }
239}
240
241template <class MemDepPred, class Impl>
242void
243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
244{
245 ThreadID tid = inst->threadNumber;
246
247 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
248
249 // Insert the MemDepEntry into the hash.
250 memDepHash.insert(
251 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
252#ifdef DEBUG
253 MemDepEntry::memdep_insert++;
254#endif
255
256 // Add the instruction to the list.
257 instList[tid].push_back(inst);
258
259 inst_entry->listIt = --(instList[tid].end());
260
261 // Might want to turn this part into an inline function or something.
262 // It's shared between both insert functions.
263 if (inst->isStore()) {
264 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
265 inst->pcState(), inst->seqNum);
266
267 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
268
269 ++insertedStores;
270 } else if (inst->isLoad()) {
271 ++insertedLoads;
272 } else {
273 panic("Unknown type! (most likely a barrier).");
274 }
275}
276
277template <class MemDepPred, class Impl>
278void
279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
280{
281 InstSeqNum barr_sn = barr_inst->seqNum;
282 // Memory barriers block loads and stores, write barriers only stores.
283 if (barr_inst->isMemBarrier()) {
284 loadBarrier = true;
285 loadBarrierSN = barr_sn;
286 storeBarrier = true;
287 storeBarrierSN = barr_sn;
288 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
289 } else if (barr_inst->isWriteBarrier()) {
290 storeBarrier = true;
291 storeBarrierSN = barr_sn;
292 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
293 }
294
295 ThreadID tid = barr_inst->threadNumber;
296
297 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
298
299 // Add the MemDepEntry to the hash.
300 memDepHash.insert(
301 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
302#ifdef DEBUG
303 MemDepEntry::memdep_insert++;
304#endif
305
306 // Add the instruction to the instruction list.
307 instList[tid].push_back(barr_inst);
308
309 inst_entry->listIt = --(instList[tid].end());
310}
311
312template <class MemDepPred, class Impl>
313void
314MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
315{
316 DPRINTF(MemDepUnit, "Marking registers as ready for "
317 "instruction PC %s [sn:%lli].\n",
318 inst->pcState(), inst->seqNum);
319
320 MemDepEntryPtr inst_entry = findInHash(inst);
321
322 inst_entry->regsReady = true;
323
324 if (inst_entry->memDepReady) {
325 DPRINTF(MemDepUnit, "Instruction has its memory "
326 "dependencies resolved, adding it to the ready list.\n");
327
328 moveToReady(inst_entry);
329 } else {
330 DPRINTF(MemDepUnit, "Instruction still waiting on "
331 "memory dependency.\n");
332 }
333}
334
335template <class MemDepPred, class Impl>
336void
337MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
338{
339 DPRINTF(MemDepUnit, "Marking non speculative "
340 "instruction PC %s as ready [sn:%lli].\n",
341 inst->pcState(), inst->seqNum);
342
343 MemDepEntryPtr inst_entry = findInHash(inst);
344
345 moveToReady(inst_entry);
346}
347
348template <class MemDepPred, class Impl>
349void
350MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
351{
352 instsToReplay.push_back(inst);
353}
354
355template <class MemDepPred, class Impl>
356void
357MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
358{
359 DynInstPtr temp_inst;
360
361 // For now this replay function replays all waiting memory ops.
362 while (!instsToReplay.empty()) {
363 temp_inst = instsToReplay.front();
364
365 MemDepEntryPtr inst_entry = findInHash(temp_inst);
366
367 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
368 temp_inst->pcState(), temp_inst->seqNum);
369
370 moveToReady(inst_entry);
371
372 instsToReplay.pop_front();
373 }
374}
375
376template <class MemDepPred, class Impl>
377void
378MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
379{
380 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
381 inst->pcState(), inst->seqNum);
382
383 ThreadID tid = inst->threadNumber;
384
385 // Remove the instruction from the hash and the list.
386 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
387
388 assert(hash_it != memDepHash.end());
389
390 instList[tid].erase((*hash_it).second->listIt);
391
392 (*hash_it).second = NULL;
393
394 memDepHash.erase(hash_it);
395#ifdef DEBUG
396 MemDepEntry::memdep_erase++;
397#endif
398}
399
400template <class MemDepPred, class Impl>
401void
402MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
403{
404 wakeDependents(inst);
405 completed(inst);
406
407 InstSeqNum barr_sn = inst->seqNum;
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35#include "debug/MemDepUnit.hh"
36#include "params/DerivO3CPU.hh"
37
38template <class MemDepPred, class Impl>
39MemDepUnit<MemDepPred, Impl>::MemDepUnit()
40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
41 storeBarrierSN(0), iqPtr(NULL)
42{
43}
44
45template <class MemDepPred, class Impl>
46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
47 : _name(params->name + ".memdepunit"),
48 depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
49 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
50{
51 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
52}
53
54template <class MemDepPred, class Impl>
55MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
56{
57 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
58
59 ListIt inst_list_it = instList[tid].begin();
60
61 MemDepHashIt hash_it;
62
63 while (!instList[tid].empty()) {
64 hash_it = memDepHash.find((*inst_list_it)->seqNum);
65
66 assert(hash_it != memDepHash.end());
67
68 memDepHash.erase(hash_it);
69
70 instList[tid].erase(inst_list_it++);
71 }
72 }
73
74#ifdef DEBUG
75 assert(MemDepEntry::memdep_count == 0);
76#endif
77}
78
79template <class MemDepPred, class Impl>
80void
81MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
82{
83 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
84
85 _name = csprintf("%s.memDep%d", params->name, tid);
86 id = tid;
87
88 depPred.init(params->SSITSize, params->LFSTSize);
89}
90
91template <class MemDepPred, class Impl>
92void
93MemDepUnit<MemDepPred, Impl>::regStats()
94{
95 insertedLoads
96 .name(name() + ".insertedLoads")
97 .desc("Number of loads inserted to the mem dependence unit.");
98
99 insertedStores
100 .name(name() + ".insertedStores")
101 .desc("Number of stores inserted to the mem dependence unit.");
102
103 conflictingLoads
104 .name(name() + ".conflictingLoads")
105 .desc("Number of conflicting loads.");
106
107 conflictingStores
108 .name(name() + ".conflictingStores")
109 .desc("Number of conflicting stores.");
110}
111
112template <class MemDepPred, class Impl>
113void
114MemDepUnit<MemDepPred, Impl>::switchOut()
115{
116 assert(instList[0].empty());
117 assert(instsToReplay.empty());
118 assert(memDepHash.empty());
119 // Clear any state.
120 for (int i = 0; i < Impl::MaxThreads; ++i) {
121 instList[i].clear();
122 }
123 instsToReplay.clear();
124 memDepHash.clear();
125}
126
127template <class MemDepPred, class Impl>
128void
129MemDepUnit<MemDepPred, Impl>::takeOverFrom()
130{
131 // Be sure to reset all state.
132 loadBarrier = storeBarrier = false;
133 loadBarrierSN = storeBarrierSN = 0;
134 depPred.clear();
135}
136
137template <class MemDepPred, class Impl>
138void
139MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
140{
141 iqPtr = iq_ptr;
142}
143
144template <class MemDepPred, class Impl>
145void
146MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
147{
148 ThreadID tid = inst->threadNumber;
149
150 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
151
152 // Add the MemDepEntry to the hash.
153 memDepHash.insert(
154 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
155#ifdef DEBUG
156 MemDepEntry::memdep_insert++;
157#endif
158
159 instList[tid].push_back(inst);
160
161 inst_entry->listIt = --(instList[tid].end());
162
163 // Check any barriers and the dependence predictor for any
164 // producing memrefs/stores.
165 InstSeqNum producing_store;
166 if (inst->isLoad() && loadBarrier) {
167 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
168 loadBarrierSN);
169 producing_store = loadBarrierSN;
170 } else if (inst->isStore() && storeBarrier) {
171 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
172 storeBarrierSN);
173 producing_store = storeBarrierSN;
174 } else {
175 producing_store = depPred.checkInst(inst->instAddr());
176 }
177
178 MemDepEntryPtr store_entry = NULL;
179
180 // If there is a producing store, try to find the entry.
181 if (producing_store != 0) {
182 DPRINTF(MemDepUnit, "Searching for producer\n");
183 MemDepHashIt hash_it = memDepHash.find(producing_store);
184
185 if (hash_it != memDepHash.end()) {
186 store_entry = (*hash_it).second;
187 DPRINTF(MemDepUnit, "Proucer found\n");
188 }
189 }
190
191 // If no store entry, then instruction can issue as soon as the registers
192 // are ready.
193 if (!store_entry) {
194 DPRINTF(MemDepUnit, "No dependency for inst PC "
195 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
196
197 inst_entry->memDepReady = true;
198
199 if (inst->readyToIssue()) {
200 inst_entry->regsReady = true;
201
202 moveToReady(inst_entry);
203 }
204 } else {
205 // Otherwise make the instruction dependent on the store/barrier.
206 DPRINTF(MemDepUnit, "Adding to dependency list; "
207 "inst PC %s is dependent on [sn:%lli].\n",
208 inst->pcState(), producing_store);
209
210 if (inst->readyToIssue()) {
211 inst_entry->regsReady = true;
212 }
213
214 // Clear the bit saying this instruction can issue.
215 inst->clearCanIssue();
216
217 // Add this instruction to the list of dependents.
218 store_entry->dependInsts.push_back(inst_entry);
219
220 if (inst->isLoad()) {
221 ++conflictingLoads;
222 } else {
223 ++conflictingStores;
224 }
225 }
226
227 if (inst->isStore()) {
228 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
229 inst->pcState(), inst->seqNum);
230
231 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
232
233 ++insertedStores;
234 } else if (inst->isLoad()) {
235 ++insertedLoads;
236 } else {
237 panic("Unknown type! (most likely a barrier).");
238 }
239}
240
241template <class MemDepPred, class Impl>
242void
243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
244{
245 ThreadID tid = inst->threadNumber;
246
247 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
248
249 // Insert the MemDepEntry into the hash.
250 memDepHash.insert(
251 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
252#ifdef DEBUG
253 MemDepEntry::memdep_insert++;
254#endif
255
256 // Add the instruction to the list.
257 instList[tid].push_back(inst);
258
259 inst_entry->listIt = --(instList[tid].end());
260
261 // Might want to turn this part into an inline function or something.
262 // It's shared between both insert functions.
263 if (inst->isStore()) {
264 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
265 inst->pcState(), inst->seqNum);
266
267 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
268
269 ++insertedStores;
270 } else if (inst->isLoad()) {
271 ++insertedLoads;
272 } else {
273 panic("Unknown type! (most likely a barrier).");
274 }
275}
276
277template <class MemDepPred, class Impl>
278void
279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
280{
281 InstSeqNum barr_sn = barr_inst->seqNum;
282 // Memory barriers block loads and stores, write barriers only stores.
283 if (barr_inst->isMemBarrier()) {
284 loadBarrier = true;
285 loadBarrierSN = barr_sn;
286 storeBarrier = true;
287 storeBarrierSN = barr_sn;
288 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
289 } else if (barr_inst->isWriteBarrier()) {
290 storeBarrier = true;
291 storeBarrierSN = barr_sn;
292 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
293 }
294
295 ThreadID tid = barr_inst->threadNumber;
296
297 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
298
299 // Add the MemDepEntry to the hash.
300 memDepHash.insert(
301 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
302#ifdef DEBUG
303 MemDepEntry::memdep_insert++;
304#endif
305
306 // Add the instruction to the instruction list.
307 instList[tid].push_back(barr_inst);
308
309 inst_entry->listIt = --(instList[tid].end());
310}
311
312template <class MemDepPred, class Impl>
313void
314MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
315{
316 DPRINTF(MemDepUnit, "Marking registers as ready for "
317 "instruction PC %s [sn:%lli].\n",
318 inst->pcState(), inst->seqNum);
319
320 MemDepEntryPtr inst_entry = findInHash(inst);
321
322 inst_entry->regsReady = true;
323
324 if (inst_entry->memDepReady) {
325 DPRINTF(MemDepUnit, "Instruction has its memory "
326 "dependencies resolved, adding it to the ready list.\n");
327
328 moveToReady(inst_entry);
329 } else {
330 DPRINTF(MemDepUnit, "Instruction still waiting on "
331 "memory dependency.\n");
332 }
333}
334
335template <class MemDepPred, class Impl>
336void
337MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
338{
339 DPRINTF(MemDepUnit, "Marking non speculative "
340 "instruction PC %s as ready [sn:%lli].\n",
341 inst->pcState(), inst->seqNum);
342
343 MemDepEntryPtr inst_entry = findInHash(inst);
344
345 moveToReady(inst_entry);
346}
347
348template <class MemDepPred, class Impl>
349void
350MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
351{
352 instsToReplay.push_back(inst);
353}
354
355template <class MemDepPred, class Impl>
356void
357MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
358{
359 DynInstPtr temp_inst;
360
361 // For now this replay function replays all waiting memory ops.
362 while (!instsToReplay.empty()) {
363 temp_inst = instsToReplay.front();
364
365 MemDepEntryPtr inst_entry = findInHash(temp_inst);
366
367 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
368 temp_inst->pcState(), temp_inst->seqNum);
369
370 moveToReady(inst_entry);
371
372 instsToReplay.pop_front();
373 }
374}
375
376template <class MemDepPred, class Impl>
377void
378MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
379{
380 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
381 inst->pcState(), inst->seqNum);
382
383 ThreadID tid = inst->threadNumber;
384
385 // Remove the instruction from the hash and the list.
386 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
387
388 assert(hash_it != memDepHash.end());
389
390 instList[tid].erase((*hash_it).second->listIt);
391
392 (*hash_it).second = NULL;
393
394 memDepHash.erase(hash_it);
395#ifdef DEBUG
396 MemDepEntry::memdep_erase++;
397#endif
398}
399
400template <class MemDepPred, class Impl>
401void
402MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
403{
404 wakeDependents(inst);
405 completed(inst);
406
407 InstSeqNum barr_sn = inst->seqNum;
408
408 DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
409 inst->seqNum);
409 if (inst->isMemBarrier()) {
410 if (inst->isMemBarrier()) {
410 assert(loadBarrier && storeBarrier);
411 if (loadBarrierSN == barr_sn)
412 loadBarrier = false;
413 if (storeBarrierSN == barr_sn)
414 storeBarrier = false;
415 } else if (inst->isWriteBarrier()) {
411 if (loadBarrierSN == barr_sn)
412 loadBarrier = false;
413 if (storeBarrierSN == barr_sn)
414 storeBarrier = false;
415 } else if (inst->isWriteBarrier()) {
416 assert(storeBarrier);
417 if (storeBarrierSN == barr_sn)
418 storeBarrier = false;
419 }
420}
421
422template <class MemDepPred, class Impl>
423void
424MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
425{
426 // Only stores and barriers have dependents.
427 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
428 return;
429 }
430
431 MemDepEntryPtr inst_entry = findInHash(inst);
432
433 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
434 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
435
436 if (!woken_inst->inst) {
437 // Potentially removed mem dep entries could be on this list
438 continue;
439 }
440
441 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
442 "[sn:%lli].\n",
443 woken_inst->inst->seqNum);
444
445 if (woken_inst->regsReady && !woken_inst->squashed) {
446 moveToReady(woken_inst);
447 } else {
448 woken_inst->memDepReady = true;
449 }
450 }
451
452 inst_entry->dependInsts.clear();
453}
454
455template <class MemDepPred, class Impl>
456void
457MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
458 ThreadID tid)
459{
460 if (!instsToReplay.empty()) {
461 ListIt replay_it = instsToReplay.begin();
462 while (replay_it != instsToReplay.end()) {
463 if ((*replay_it)->threadNumber == tid &&
464 (*replay_it)->seqNum > squashed_num) {
465 instsToReplay.erase(replay_it++);
466 } else {
467 ++replay_it;
468 }
469 }
470 }
471
472 ListIt squash_it = instList[tid].end();
473 --squash_it;
474
475 MemDepHashIt hash_it;
476
477 while (!instList[tid].empty() &&
478 (*squash_it)->seqNum > squashed_num) {
479
480 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
481 (*squash_it)->seqNum);
482
416 if (storeBarrierSN == barr_sn)
417 storeBarrier = false;
418 }
419}
420
421template <class MemDepPred, class Impl>
422void
423MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
424{
425 // Only stores and barriers have dependents.
426 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
427 return;
428 }
429
430 MemDepEntryPtr inst_entry = findInHash(inst);
431
432 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
433 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
434
435 if (!woken_inst->inst) {
436 // Potentially removed mem dep entries could be on this list
437 continue;
438 }
439
440 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
441 "[sn:%lli].\n",
442 woken_inst->inst->seqNum);
443
444 if (woken_inst->regsReady && !woken_inst->squashed) {
445 moveToReady(woken_inst);
446 } else {
447 woken_inst->memDepReady = true;
448 }
449 }
450
451 inst_entry->dependInsts.clear();
452}
453
454template <class MemDepPred, class Impl>
455void
456MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
457 ThreadID tid)
458{
459 if (!instsToReplay.empty()) {
460 ListIt replay_it = instsToReplay.begin();
461 while (replay_it != instsToReplay.end()) {
462 if ((*replay_it)->threadNumber == tid &&
463 (*replay_it)->seqNum > squashed_num) {
464 instsToReplay.erase(replay_it++);
465 } else {
466 ++replay_it;
467 }
468 }
469 }
470
471 ListIt squash_it = instList[tid].end();
472 --squash_it;
473
474 MemDepHashIt hash_it;
475
476 while (!instList[tid].empty() &&
477 (*squash_it)->seqNum > squashed_num) {
478
479 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
480 (*squash_it)->seqNum);
481
482 if ((*squash_it)->seqNum == loadBarrierSN)
483 loadBarrier = false;
484
485 if ((*squash_it)->seqNum == storeBarrierSN)
486 storeBarrier = false;
487
483 hash_it = memDepHash.find((*squash_it)->seqNum);
484
485 assert(hash_it != memDepHash.end());
486
487 (*hash_it).second->squashed = true;
488
489 (*hash_it).second = NULL;
490
491 memDepHash.erase(hash_it);
492#ifdef DEBUG
493 MemDepEntry::memdep_erase++;
494#endif
495
496 instList[tid].erase(squash_it--);
497 }
498
499 // Tell the dependency predictor to squash as well.
500 depPred.squash(squashed_num, tid);
501}
502
503template <class MemDepPred, class Impl>
504void
505MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
506 DynInstPtr &violating_load)
507{
508 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
509 " load: %#x, store: %#x\n", violating_load->instAddr(),
510 store_inst->instAddr());
511 // Tell the memory dependence unit of the violation.
488 hash_it = memDepHash.find((*squash_it)->seqNum);
489
490 assert(hash_it != memDepHash.end());
491
492 (*hash_it).second->squashed = true;
493
494 (*hash_it).second = NULL;
495
496 memDepHash.erase(hash_it);
497#ifdef DEBUG
498 MemDepEntry::memdep_erase++;
499#endif
500
501 instList[tid].erase(squash_it--);
502 }
503
504 // Tell the dependency predictor to squash as well.
505 depPred.squash(squashed_num, tid);
506}
507
508template <class MemDepPred, class Impl>
509void
510MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
511 DynInstPtr &violating_load)
512{
513 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
514 " load: %#x, store: %#x\n", violating_load->instAddr(),
515 store_inst->instAddr());
516 // Tell the memory dependence unit of the violation.
512 depPred.violation(violating_load->instAddr(), store_inst->instAddr());
517 depPred.violation(store_inst->instAddr(), violating_load->instAddr());
513}
514
515template <class MemDepPred, class Impl>
516void
517MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
518{
519 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
520 inst->instAddr(), inst->seqNum);
521
522 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
523}
524
525template <class MemDepPred, class Impl>
526inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
527MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
528{
529 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
530
531 assert(hash_it != memDepHash.end());
532
533 return (*hash_it).second;
534}
535
536template <class MemDepPred, class Impl>
537inline void
538MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
539{
540 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
541 "to the ready list.\n", woken_inst_entry->inst->seqNum);
542
543 assert(!woken_inst_entry->squashed);
544
545 iqPtr->addReadyMemInst(woken_inst_entry->inst);
546}
547
548
549template <class MemDepPred, class Impl>
550void
551MemDepUnit<MemDepPred, Impl>::dumpLists()
552{
553 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
554 cprintf("Instruction list %i size: %i\n",
555 tid, instList[tid].size());
556
557 ListIt inst_list_it = instList[tid].begin();
558 int num = 0;
559
560 while (inst_list_it != instList[tid].end()) {
561 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
562 "Squashed:%i\n\n",
563 num, (*inst_list_it)->pcState(),
564 (*inst_list_it)->seqNum,
565 (*inst_list_it)->threadNumber,
566 (*inst_list_it)->isIssued(),
567 (*inst_list_it)->isSquashed());
568 inst_list_it++;
569 ++num;
570 }
571 }
572
573 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
574
575#ifdef DEBUG
576 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
577#endif
578}
518}
519
520template <class MemDepPred, class Impl>
521void
522MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
523{
524 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
525 inst->instAddr(), inst->seqNum);
526
527 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
528}
529
530template <class MemDepPred, class Impl>
531inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
532MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
533{
534 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
535
536 assert(hash_it != memDepHash.end());
537
538 return (*hash_it).second;
539}
540
541template <class MemDepPred, class Impl>
542inline void
543MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
544{
545 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
546 "to the ready list.\n", woken_inst_entry->inst->seqNum);
547
548 assert(!woken_inst_entry->squashed);
549
550 iqPtr->addReadyMemInst(woken_inst_entry->inst);
551}
552
553
554template <class MemDepPred, class Impl>
555void
556MemDepUnit<MemDepPred, Impl>::dumpLists()
557{
558 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
559 cprintf("Instruction list %i size: %i\n",
560 tid, instList[tid].size());
561
562 ListIt inst_list_it = instList[tid].begin();
563 int num = 0;
564
565 while (inst_list_it != instList[tid].end()) {
566 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
567 "Squashed:%i\n\n",
568 num, (*inst_list_it)->pcState(),
569 (*inst_list_it)->seqNum,
570 (*inst_list_it)->threadNumber,
571 (*inst_list_it)->isIssued(),
572 (*inst_list_it)->isSquashed());
573 inst_list_it++;
574 ++num;
575 }
576 }
577
578 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
579
580#ifdef DEBUG
581 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
582#endif
583}