35#include "params/DerivO3CPU.hh" 36 37template <class MemDepPred, class Impl> 38MemDepUnit<MemDepPred, Impl>::MemDepUnit() 39 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 40 storeBarrierSN(0), iqPtr(NULL) 41{ 42} 43 44template <class MemDepPred, class Impl> 45MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 46 : _name(params->name + ".memdepunit"), 47 depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 48 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 49{ 50 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 51} 52 53template <class MemDepPred, class Impl> 54MemDepUnit<MemDepPred, Impl>::~MemDepUnit() 55{ 56 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 57 58 ListIt inst_list_it = instList[tid].begin(); 59 60 MemDepHashIt hash_it; 61 62 while (!instList[tid].empty()) { 63 hash_it = memDepHash.find((*inst_list_it)->seqNum); 64 65 assert(hash_it != memDepHash.end()); 66 67 memDepHash.erase(hash_it); 68 69 instList[tid].erase(inst_list_it++); 70 } 71 } 72 73#ifdef DEBUG 74 assert(MemDepEntry::memdep_count == 0); 75#endif 76} 77 78template <class MemDepPred, class Impl> 79void 80MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 81{ 82 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 83 84 _name = csprintf("%s.memDep%d", params->name, tid); 85 id = tid; 86 87 depPred.init(params->SSITSize, params->LFSTSize); 88} 89 90template <class MemDepPred, class Impl> 91void 92MemDepUnit<MemDepPred, Impl>::regStats() 93{ 94 insertedLoads 95 .name(name() + ".insertedLoads") 96 .desc("Number of loads inserted to the mem dependence unit."); 97 98 insertedStores 99 .name(name() + ".insertedStores") 100 .desc("Number of stores inserted to the mem dependence unit."); 101 102 conflictingLoads 103 .name(name() + ".conflictingLoads") 104 .desc("Number of conflicting loads."); 105 106 conflictingStores 107 .name(name() + ".conflictingStores") 108 .desc("Number of conflicting stores."); 109} 110 111template <class MemDepPred, class Impl> 112void 113MemDepUnit<MemDepPred, Impl>::switchOut() 114{ 115 assert(instList[0].empty()); 116 assert(instsToReplay.empty()); 117 assert(memDepHash.empty()); 118 // Clear any state. 119 for (int i = 0; i < Impl::MaxThreads; ++i) { 120 instList[i].clear(); 121 } 122 instsToReplay.clear(); 123 memDepHash.clear(); 124} 125 126template <class MemDepPred, class Impl> 127void 128MemDepUnit<MemDepPred, Impl>::takeOverFrom() 129{ 130 // Be sure to reset all state. 131 loadBarrier = storeBarrier = false; 132 loadBarrierSN = storeBarrierSN = 0; 133 depPred.clear(); 134} 135 136template <class MemDepPred, class Impl> 137void 138MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 139{ 140 iqPtr = iq_ptr; 141} 142 143template <class MemDepPred, class Impl> 144void 145MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 146{ 147 ThreadID tid = inst->threadNumber; 148 149 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 150 151 // Add the MemDepEntry to the hash. 152 memDepHash.insert( 153 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 154#ifdef DEBUG 155 MemDepEntry::memdep_insert++; 156#endif 157 158 instList[tid].push_back(inst); 159 160 inst_entry->listIt = --(instList[tid].end()); 161 162 // Check any barriers and the dependence predictor for any 163 // producing memrefs/stores. 164 InstSeqNum producing_store; 165 if (inst->isLoad() && loadBarrier) { 166 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 167 loadBarrierSN); 168 producing_store = loadBarrierSN; 169 } else if (inst->isStore() && storeBarrier) { 170 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 171 storeBarrierSN); 172 producing_store = storeBarrierSN; 173 } else { 174 producing_store = depPred.checkInst(inst->instAddr()); 175 } 176 177 MemDepEntryPtr store_entry = NULL; 178 179 // If there is a producing store, try to find the entry. 180 if (producing_store != 0) { 181 DPRINTF(MemDepUnit, "Searching for producer\n"); 182 MemDepHashIt hash_it = memDepHash.find(producing_store); 183 184 if (hash_it != memDepHash.end()) { 185 store_entry = (*hash_it).second; 186 DPRINTF(MemDepUnit, "Proucer found\n"); 187 } 188 } 189 190 // If no store entry, then instruction can issue as soon as the registers 191 // are ready. 192 if (!store_entry) { 193 DPRINTF(MemDepUnit, "No dependency for inst PC " 194 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 195 196 inst_entry->memDepReady = true; 197 198 if (inst->readyToIssue()) { 199 inst_entry->regsReady = true; 200 201 moveToReady(inst_entry); 202 } 203 } else { 204 // Otherwise make the instruction dependent on the store/barrier. 205 DPRINTF(MemDepUnit, "Adding to dependency list; " 206 "inst PC %s is dependent on [sn:%lli].\n", 207 inst->pcState(), producing_store); 208 209 if (inst->readyToIssue()) { 210 inst_entry->regsReady = true; 211 } 212 213 // Clear the bit saying this instruction can issue. 214 inst->clearCanIssue(); 215 216 // Add this instruction to the list of dependents. 217 store_entry->dependInsts.push_back(inst_entry); 218 219 if (inst->isLoad()) { 220 ++conflictingLoads; 221 } else { 222 ++conflictingStores; 223 } 224 } 225 226 if (inst->isStore()) { 227 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 228 inst->pcState(), inst->seqNum); 229 230 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 231 232 ++insertedStores; 233 } else if (inst->isLoad()) { 234 ++insertedLoads; 235 } else { 236 panic("Unknown type! (most likely a barrier)."); 237 } 238} 239 240template <class MemDepPred, class Impl> 241void 242MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 243{ 244 ThreadID tid = inst->threadNumber; 245 246 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 247 248 // Insert the MemDepEntry into the hash. 249 memDepHash.insert( 250 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 251#ifdef DEBUG 252 MemDepEntry::memdep_insert++; 253#endif 254 255 // Add the instruction to the list. 256 instList[tid].push_back(inst); 257 258 inst_entry->listIt = --(instList[tid].end()); 259 260 // Might want to turn this part into an inline function or something. 261 // It's shared between both insert functions. 262 if (inst->isStore()) { 263 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 264 inst->pcState(), inst->seqNum); 265 266 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 267 268 ++insertedStores; 269 } else if (inst->isLoad()) { 270 ++insertedLoads; 271 } else { 272 panic("Unknown type! (most likely a barrier)."); 273 } 274} 275 276template <class MemDepPred, class Impl> 277void 278MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 279{ 280 InstSeqNum barr_sn = barr_inst->seqNum; 281 // Memory barriers block loads and stores, write barriers only stores. 282 if (barr_inst->isMemBarrier()) { 283 loadBarrier = true; 284 loadBarrierSN = barr_sn; 285 storeBarrier = true; 286 storeBarrierSN = barr_sn; 287 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 288 } else if (barr_inst->isWriteBarrier()) { 289 storeBarrier = true; 290 storeBarrierSN = barr_sn; 291 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 292 } 293 294 ThreadID tid = barr_inst->threadNumber; 295 296 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 297 298 // Add the MemDepEntry to the hash. 299 memDepHash.insert( 300 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 301#ifdef DEBUG 302 MemDepEntry::memdep_insert++; 303#endif 304 305 // Add the instruction to the instruction list. 306 instList[tid].push_back(barr_inst); 307 308 inst_entry->listIt = --(instList[tid].end()); 309} 310 311template <class MemDepPred, class Impl> 312void 313MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 314{ 315 DPRINTF(MemDepUnit, "Marking registers as ready for " 316 "instruction PC %s [sn:%lli].\n", 317 inst->pcState(), inst->seqNum); 318 319 MemDepEntryPtr inst_entry = findInHash(inst); 320 321 inst_entry->regsReady = true; 322 323 if (inst_entry->memDepReady) { 324 DPRINTF(MemDepUnit, "Instruction has its memory " 325 "dependencies resolved, adding it to the ready list.\n"); 326 327 moveToReady(inst_entry); 328 } else { 329 DPRINTF(MemDepUnit, "Instruction still waiting on " 330 "memory dependency.\n"); 331 } 332} 333 334template <class MemDepPred, class Impl> 335void 336MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 337{ 338 DPRINTF(MemDepUnit, "Marking non speculative " 339 "instruction PC %s as ready [sn:%lli].\n", 340 inst->pcState(), inst->seqNum); 341 342 MemDepEntryPtr inst_entry = findInHash(inst); 343 344 moveToReady(inst_entry); 345} 346 347template <class MemDepPred, class Impl> 348void 349MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 350{ 351 instsToReplay.push_back(inst); 352} 353 354template <class MemDepPred, class Impl> 355void 356MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 357{ 358 DynInstPtr temp_inst; 359 360 // For now this replay function replays all waiting memory ops. 361 while (!instsToReplay.empty()) { 362 temp_inst = instsToReplay.front(); 363 364 MemDepEntryPtr inst_entry = findInHash(temp_inst); 365 366 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 367 temp_inst->pcState(), temp_inst->seqNum); 368 369 moveToReady(inst_entry); 370 371 instsToReplay.pop_front(); 372 } 373} 374 375template <class MemDepPred, class Impl> 376void 377MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 378{ 379 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 380 inst->pcState(), inst->seqNum); 381 382 ThreadID tid = inst->threadNumber; 383 384 // Remove the instruction from the hash and the list. 385 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 386 387 assert(hash_it != memDepHash.end()); 388 389 instList[tid].erase((*hash_it).second->listIt); 390 391 (*hash_it).second = NULL; 392 393 memDepHash.erase(hash_it); 394#ifdef DEBUG 395 MemDepEntry::memdep_erase++; 396#endif 397} 398 399template <class MemDepPred, class Impl> 400void 401MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 402{ 403 wakeDependents(inst); 404 completed(inst); 405 406 InstSeqNum barr_sn = inst->seqNum; 407 408 if (inst->isMemBarrier()) { 409 assert(loadBarrier && storeBarrier); 410 if (loadBarrierSN == barr_sn) 411 loadBarrier = false; 412 if (storeBarrierSN == barr_sn) 413 storeBarrier = false; 414 } else if (inst->isWriteBarrier()) { 415 assert(storeBarrier); 416 if (storeBarrierSN == barr_sn) 417 storeBarrier = false; 418 } 419} 420 421template <class MemDepPred, class Impl> 422void 423MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 424{ 425 // Only stores and barriers have dependents. 426 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 427 return; 428 } 429 430 MemDepEntryPtr inst_entry = findInHash(inst); 431 432 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 433 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 434 435 if (!woken_inst->inst) { 436 // Potentially removed mem dep entries could be on this list 437 continue; 438 } 439 440 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 441 "[sn:%lli].\n", 442 woken_inst->inst->seqNum); 443 444 if (woken_inst->regsReady && !woken_inst->squashed) { 445 moveToReady(woken_inst); 446 } else { 447 woken_inst->memDepReady = true; 448 } 449 } 450 451 inst_entry->dependInsts.clear(); 452} 453 454template <class MemDepPred, class Impl> 455void 456MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 457 ThreadID tid) 458{ 459 if (!instsToReplay.empty()) { 460 ListIt replay_it = instsToReplay.begin(); 461 while (replay_it != instsToReplay.end()) { 462 if ((*replay_it)->threadNumber == tid && 463 (*replay_it)->seqNum > squashed_num) { 464 instsToReplay.erase(replay_it++); 465 } else { 466 ++replay_it; 467 } 468 } 469 } 470 471 ListIt squash_it = instList[tid].end(); 472 --squash_it; 473 474 MemDepHashIt hash_it; 475 476 while (!instList[tid].empty() && 477 (*squash_it)->seqNum > squashed_num) { 478 479 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 480 (*squash_it)->seqNum); 481 482 hash_it = memDepHash.find((*squash_it)->seqNum); 483 484 assert(hash_it != memDepHash.end()); 485 486 (*hash_it).second->squashed = true; 487 488 (*hash_it).second = NULL; 489 490 memDepHash.erase(hash_it); 491#ifdef DEBUG 492 MemDepEntry::memdep_erase++; 493#endif 494 495 instList[tid].erase(squash_it--); 496 } 497 498 // Tell the dependency predictor to squash as well. 499 depPred.squash(squashed_num, tid); 500} 501 502template <class MemDepPred, class Impl> 503void 504MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 505 DynInstPtr &violating_load) 506{ 507 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 508 " load: %#x, store: %#x\n", violating_load->instAddr(), 509 store_inst->instAddr()); 510 // Tell the memory dependence unit of the violation. 511 depPred.violation(violating_load->instAddr(), store_inst->instAddr()); 512} 513 514template <class MemDepPred, class Impl> 515void 516MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 517{ 518 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 519 inst->instAddr(), inst->seqNum); 520 521 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 522} 523 524template <class MemDepPred, class Impl> 525inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 526MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 527{ 528 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 529 530 assert(hash_it != memDepHash.end()); 531 532 return (*hash_it).second; 533} 534 535template <class MemDepPred, class Impl> 536inline void 537MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 538{ 539 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 540 "to the ready list.\n", woken_inst_entry->inst->seqNum); 541 542 assert(!woken_inst_entry->squashed); 543 544 iqPtr->addReadyMemInst(woken_inst_entry->inst); 545} 546 547 548template <class MemDepPred, class Impl> 549void 550MemDepUnit<MemDepPred, Impl>::dumpLists() 551{ 552 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 553 cprintf("Instruction list %i size: %i\n", 554 tid, instList[tid].size()); 555 556 ListIt inst_list_it = instList[tid].begin(); 557 int num = 0; 558 559 while (inst_list_it != instList[tid].end()) { 560 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 561 "Squashed:%i\n\n", 562 num, (*inst_list_it)->pcState(), 563 (*inst_list_it)->seqNum, 564 (*inst_list_it)->threadNumber, 565 (*inst_list_it)->isIssued(), 566 (*inst_list_it)->isSquashed()); 567 inst_list_it++; 568 ++num; 569 } 570 } 571 572 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 573 574#ifdef DEBUG 575 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 576#endif 577}
| 36#include "params/DerivO3CPU.hh" 37 38template <class MemDepPred, class Impl> 39MemDepUnit<MemDepPred, Impl>::MemDepUnit() 40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 41 storeBarrierSN(0), iqPtr(NULL) 42{ 43} 44 45template <class MemDepPred, class Impl> 46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 47 : _name(params->name + ".memdepunit"), 48 depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 49 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 50{ 51 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 52} 53 54template <class MemDepPred, class Impl> 55MemDepUnit<MemDepPred, Impl>::~MemDepUnit() 56{ 57 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 58 59 ListIt inst_list_it = instList[tid].begin(); 60 61 MemDepHashIt hash_it; 62 63 while (!instList[tid].empty()) { 64 hash_it = memDepHash.find((*inst_list_it)->seqNum); 65 66 assert(hash_it != memDepHash.end()); 67 68 memDepHash.erase(hash_it); 69 70 instList[tid].erase(inst_list_it++); 71 } 72 } 73 74#ifdef DEBUG 75 assert(MemDepEntry::memdep_count == 0); 76#endif 77} 78 79template <class MemDepPred, class Impl> 80void 81MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 82{ 83 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 84 85 _name = csprintf("%s.memDep%d", params->name, tid); 86 id = tid; 87 88 depPred.init(params->SSITSize, params->LFSTSize); 89} 90 91template <class MemDepPred, class Impl> 92void 93MemDepUnit<MemDepPred, Impl>::regStats() 94{ 95 insertedLoads 96 .name(name() + ".insertedLoads") 97 .desc("Number of loads inserted to the mem dependence unit."); 98 99 insertedStores 100 .name(name() + ".insertedStores") 101 .desc("Number of stores inserted to the mem dependence unit."); 102 103 conflictingLoads 104 .name(name() + ".conflictingLoads") 105 .desc("Number of conflicting loads."); 106 107 conflictingStores 108 .name(name() + ".conflictingStores") 109 .desc("Number of conflicting stores."); 110} 111 112template <class MemDepPred, class Impl> 113void 114MemDepUnit<MemDepPred, Impl>::switchOut() 115{ 116 assert(instList[0].empty()); 117 assert(instsToReplay.empty()); 118 assert(memDepHash.empty()); 119 // Clear any state. 120 for (int i = 0; i < Impl::MaxThreads; ++i) { 121 instList[i].clear(); 122 } 123 instsToReplay.clear(); 124 memDepHash.clear(); 125} 126 127template <class MemDepPred, class Impl> 128void 129MemDepUnit<MemDepPred, Impl>::takeOverFrom() 130{ 131 // Be sure to reset all state. 132 loadBarrier = storeBarrier = false; 133 loadBarrierSN = storeBarrierSN = 0; 134 depPred.clear(); 135} 136 137template <class MemDepPred, class Impl> 138void 139MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 140{ 141 iqPtr = iq_ptr; 142} 143 144template <class MemDepPred, class Impl> 145void 146MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 147{ 148 ThreadID tid = inst->threadNumber; 149 150 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 151 152 // Add the MemDepEntry to the hash. 153 memDepHash.insert( 154 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 155#ifdef DEBUG 156 MemDepEntry::memdep_insert++; 157#endif 158 159 instList[tid].push_back(inst); 160 161 inst_entry->listIt = --(instList[tid].end()); 162 163 // Check any barriers and the dependence predictor for any 164 // producing memrefs/stores. 165 InstSeqNum producing_store; 166 if (inst->isLoad() && loadBarrier) { 167 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 168 loadBarrierSN); 169 producing_store = loadBarrierSN; 170 } else if (inst->isStore() && storeBarrier) { 171 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 172 storeBarrierSN); 173 producing_store = storeBarrierSN; 174 } else { 175 producing_store = depPred.checkInst(inst->instAddr()); 176 } 177 178 MemDepEntryPtr store_entry = NULL; 179 180 // If there is a producing store, try to find the entry. 181 if (producing_store != 0) { 182 DPRINTF(MemDepUnit, "Searching for producer\n"); 183 MemDepHashIt hash_it = memDepHash.find(producing_store); 184 185 if (hash_it != memDepHash.end()) { 186 store_entry = (*hash_it).second; 187 DPRINTF(MemDepUnit, "Proucer found\n"); 188 } 189 } 190 191 // If no store entry, then instruction can issue as soon as the registers 192 // are ready. 193 if (!store_entry) { 194 DPRINTF(MemDepUnit, "No dependency for inst PC " 195 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 196 197 inst_entry->memDepReady = true; 198 199 if (inst->readyToIssue()) { 200 inst_entry->regsReady = true; 201 202 moveToReady(inst_entry); 203 } 204 } else { 205 // Otherwise make the instruction dependent on the store/barrier. 206 DPRINTF(MemDepUnit, "Adding to dependency list; " 207 "inst PC %s is dependent on [sn:%lli].\n", 208 inst->pcState(), producing_store); 209 210 if (inst->readyToIssue()) { 211 inst_entry->regsReady = true; 212 } 213 214 // Clear the bit saying this instruction can issue. 215 inst->clearCanIssue(); 216 217 // Add this instruction to the list of dependents. 218 store_entry->dependInsts.push_back(inst_entry); 219 220 if (inst->isLoad()) { 221 ++conflictingLoads; 222 } else { 223 ++conflictingStores; 224 } 225 } 226 227 if (inst->isStore()) { 228 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 229 inst->pcState(), inst->seqNum); 230 231 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 232 233 ++insertedStores; 234 } else if (inst->isLoad()) { 235 ++insertedLoads; 236 } else { 237 panic("Unknown type! (most likely a barrier)."); 238 } 239} 240 241template <class MemDepPred, class Impl> 242void 243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 244{ 245 ThreadID tid = inst->threadNumber; 246 247 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 248 249 // Insert the MemDepEntry into the hash. 250 memDepHash.insert( 251 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 252#ifdef DEBUG 253 MemDepEntry::memdep_insert++; 254#endif 255 256 // Add the instruction to the list. 257 instList[tid].push_back(inst); 258 259 inst_entry->listIt = --(instList[tid].end()); 260 261 // Might want to turn this part into an inline function or something. 262 // It's shared between both insert functions. 263 if (inst->isStore()) { 264 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 265 inst->pcState(), inst->seqNum); 266 267 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 268 269 ++insertedStores; 270 } else if (inst->isLoad()) { 271 ++insertedLoads; 272 } else { 273 panic("Unknown type! (most likely a barrier)."); 274 } 275} 276 277template <class MemDepPred, class Impl> 278void 279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 280{ 281 InstSeqNum barr_sn = barr_inst->seqNum; 282 // Memory barriers block loads and stores, write barriers only stores. 283 if (barr_inst->isMemBarrier()) { 284 loadBarrier = true; 285 loadBarrierSN = barr_sn; 286 storeBarrier = true; 287 storeBarrierSN = barr_sn; 288 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 289 } else if (barr_inst->isWriteBarrier()) { 290 storeBarrier = true; 291 storeBarrierSN = barr_sn; 292 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 293 } 294 295 ThreadID tid = barr_inst->threadNumber; 296 297 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 298 299 // Add the MemDepEntry to the hash. 300 memDepHash.insert( 301 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 302#ifdef DEBUG 303 MemDepEntry::memdep_insert++; 304#endif 305 306 // Add the instruction to the instruction list. 307 instList[tid].push_back(barr_inst); 308 309 inst_entry->listIt = --(instList[tid].end()); 310} 311 312template <class MemDepPred, class Impl> 313void 314MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 315{ 316 DPRINTF(MemDepUnit, "Marking registers as ready for " 317 "instruction PC %s [sn:%lli].\n", 318 inst->pcState(), inst->seqNum); 319 320 MemDepEntryPtr inst_entry = findInHash(inst); 321 322 inst_entry->regsReady = true; 323 324 if (inst_entry->memDepReady) { 325 DPRINTF(MemDepUnit, "Instruction has its memory " 326 "dependencies resolved, adding it to the ready list.\n"); 327 328 moveToReady(inst_entry); 329 } else { 330 DPRINTF(MemDepUnit, "Instruction still waiting on " 331 "memory dependency.\n"); 332 } 333} 334 335template <class MemDepPred, class Impl> 336void 337MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 338{ 339 DPRINTF(MemDepUnit, "Marking non speculative " 340 "instruction PC %s as ready [sn:%lli].\n", 341 inst->pcState(), inst->seqNum); 342 343 MemDepEntryPtr inst_entry = findInHash(inst); 344 345 moveToReady(inst_entry); 346} 347 348template <class MemDepPred, class Impl> 349void 350MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 351{ 352 instsToReplay.push_back(inst); 353} 354 355template <class MemDepPred, class Impl> 356void 357MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 358{ 359 DynInstPtr temp_inst; 360 361 // For now this replay function replays all waiting memory ops. 362 while (!instsToReplay.empty()) { 363 temp_inst = instsToReplay.front(); 364 365 MemDepEntryPtr inst_entry = findInHash(temp_inst); 366 367 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 368 temp_inst->pcState(), temp_inst->seqNum); 369 370 moveToReady(inst_entry); 371 372 instsToReplay.pop_front(); 373 } 374} 375 376template <class MemDepPred, class Impl> 377void 378MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 379{ 380 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 381 inst->pcState(), inst->seqNum); 382 383 ThreadID tid = inst->threadNumber; 384 385 // Remove the instruction from the hash and the list. 386 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 387 388 assert(hash_it != memDepHash.end()); 389 390 instList[tid].erase((*hash_it).second->listIt); 391 392 (*hash_it).second = NULL; 393 394 memDepHash.erase(hash_it); 395#ifdef DEBUG 396 MemDepEntry::memdep_erase++; 397#endif 398} 399 400template <class MemDepPred, class Impl> 401void 402MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 403{ 404 wakeDependents(inst); 405 completed(inst); 406 407 InstSeqNum barr_sn = inst->seqNum; 408 409 if (inst->isMemBarrier()) { 410 assert(loadBarrier && storeBarrier); 411 if (loadBarrierSN == barr_sn) 412 loadBarrier = false; 413 if (storeBarrierSN == barr_sn) 414 storeBarrier = false; 415 } else if (inst->isWriteBarrier()) { 416 assert(storeBarrier); 417 if (storeBarrierSN == barr_sn) 418 storeBarrier = false; 419 } 420} 421 422template <class MemDepPred, class Impl> 423void 424MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 425{ 426 // Only stores and barriers have dependents. 427 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 428 return; 429 } 430 431 MemDepEntryPtr inst_entry = findInHash(inst); 432 433 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 434 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 435 436 if (!woken_inst->inst) { 437 // Potentially removed mem dep entries could be on this list 438 continue; 439 } 440 441 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 442 "[sn:%lli].\n", 443 woken_inst->inst->seqNum); 444 445 if (woken_inst->regsReady && !woken_inst->squashed) { 446 moveToReady(woken_inst); 447 } else { 448 woken_inst->memDepReady = true; 449 } 450 } 451 452 inst_entry->dependInsts.clear(); 453} 454 455template <class MemDepPred, class Impl> 456void 457MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 458 ThreadID tid) 459{ 460 if (!instsToReplay.empty()) { 461 ListIt replay_it = instsToReplay.begin(); 462 while (replay_it != instsToReplay.end()) { 463 if ((*replay_it)->threadNumber == tid && 464 (*replay_it)->seqNum > squashed_num) { 465 instsToReplay.erase(replay_it++); 466 } else { 467 ++replay_it; 468 } 469 } 470 } 471 472 ListIt squash_it = instList[tid].end(); 473 --squash_it; 474 475 MemDepHashIt hash_it; 476 477 while (!instList[tid].empty() && 478 (*squash_it)->seqNum > squashed_num) { 479 480 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 481 (*squash_it)->seqNum); 482 483 hash_it = memDepHash.find((*squash_it)->seqNum); 484 485 assert(hash_it != memDepHash.end()); 486 487 (*hash_it).second->squashed = true; 488 489 (*hash_it).second = NULL; 490 491 memDepHash.erase(hash_it); 492#ifdef DEBUG 493 MemDepEntry::memdep_erase++; 494#endif 495 496 instList[tid].erase(squash_it--); 497 } 498 499 // Tell the dependency predictor to squash as well. 500 depPred.squash(squashed_num, tid); 501} 502 503template <class MemDepPred, class Impl> 504void 505MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 506 DynInstPtr &violating_load) 507{ 508 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 509 " load: %#x, store: %#x\n", violating_load->instAddr(), 510 store_inst->instAddr()); 511 // Tell the memory dependence unit of the violation. 512 depPred.violation(violating_load->instAddr(), store_inst->instAddr()); 513} 514 515template <class MemDepPred, class Impl> 516void 517MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 518{ 519 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 520 inst->instAddr(), inst->seqNum); 521 522 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 523} 524 525template <class MemDepPred, class Impl> 526inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 527MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 528{ 529 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 530 531 assert(hash_it != memDepHash.end()); 532 533 return (*hash_it).second; 534} 535 536template <class MemDepPred, class Impl> 537inline void 538MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 539{ 540 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 541 "to the ready list.\n", woken_inst_entry->inst->seqNum); 542 543 assert(!woken_inst_entry->squashed); 544 545 iqPtr->addReadyMemInst(woken_inst_entry->inst); 546} 547 548 549template <class MemDepPred, class Impl> 550void 551MemDepUnit<MemDepPred, Impl>::dumpLists() 552{ 553 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 554 cprintf("Instruction list %i size: %i\n", 555 tid, instList[tid].size()); 556 557 ListIt inst_list_it = instList[tid].begin(); 558 int num = 0; 559 560 while (inst_list_it != instList[tid].end()) { 561 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 562 "Squashed:%i\n\n", 563 num, (*inst_list_it)->pcState(), 564 (*inst_list_it)->seqNum, 565 (*inst_list_it)->threadNumber, 566 (*inst_list_it)->isIssued(), 567 (*inst_list_it)->isSquashed()); 568 inst_list_it++; 569 ++num; 570 } 571 } 572 573 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 574 575#ifdef DEBUG 576 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 577#endif 578}
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