1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include <map> 32 33#include "cpu/o3/inst_queue.hh" 34#include "cpu/o3/mem_dep_unit.hh" 35 36#include "params/DerivO3CPU.hh" 37 38template <class MemDepPred, class Impl> 39MemDepUnit<MemDepPred, Impl>::MemDepUnit() 40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 41 storeBarrierSN(0), iqPtr(NULL) 42{ 43} 44 45template <class MemDepPred, class Impl> 46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include <map> 32 33#include "cpu/o3/inst_queue.hh" 34#include "cpu/o3/mem_dep_unit.hh" 35 36#include "params/DerivO3CPU.hh" 37 38template <class MemDepPred, class Impl> 39MemDepUnit<MemDepPred, Impl>::MemDepUnit() 40 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 41 storeBarrierSN(0), iqPtr(NULL) 42{ 43} 44 45template <class MemDepPred, class Impl> 46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
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114 .desc("Number of conflicting stores."); 115} 116 117template <class MemDepPred, class Impl> 118void 119MemDepUnit<MemDepPred, Impl>::switchOut() 120{ 121 assert(instList[0].empty()); 122 assert(instsToReplay.empty()); 123 assert(memDepHash.empty()); 124 // Clear any state. 125 for (int i = 0; i < Impl::MaxThreads; ++i) { 126 instList[i].clear(); 127 } 128 instsToReplay.clear(); 129 memDepHash.clear(); 130} 131 132template <class MemDepPred, class Impl> 133void 134MemDepUnit<MemDepPred, Impl>::takeOverFrom() 135{ 136 // Be sure to reset all state. 137 loadBarrier = storeBarrier = false; 138 loadBarrierSN = storeBarrierSN = 0; 139 depPred.clear(); 140} 141 142template <class MemDepPred, class Impl> 143void 144MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 145{ 146 iqPtr = iq_ptr; 147} 148 149template <class MemDepPred, class Impl> 150void 151MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 152{ 153 unsigned tid = inst->threadNumber; 154 155 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 156 157 // Add the MemDepEntry to the hash. 158 memDepHash.insert( 159 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 160#ifdef DEBUG 161 MemDepEntry::memdep_insert++; 162#endif 163 164 instList[tid].push_back(inst); 165 166 inst_entry->listIt = --(instList[tid].end()); 167 168 // Check any barriers and the dependence predictor for any 169 // producing memrefs/stores. 170 InstSeqNum producing_store; 171 if (inst->isLoad() && loadBarrier) { 172 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 173 loadBarrierSN); 174 producing_store = loadBarrierSN; 175 } else if (inst->isStore() && storeBarrier) { 176 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 177 storeBarrierSN); 178 producing_store = storeBarrierSN; 179 } else { 180 producing_store = depPred.checkInst(inst->readPC()); 181 } 182 183 MemDepEntryPtr store_entry = NULL; 184 185 // If there is a producing store, try to find the entry. 186 if (producing_store != 0) { 187 DPRINTF(MemDepUnit, "Searching for producer\n"); 188 MemDepHashIt hash_it = memDepHash.find(producing_store); 189 190 if (hash_it != memDepHash.end()) { 191 store_entry = (*hash_it).second; 192 DPRINTF(MemDepUnit, "Proucer found\n"); 193 } 194 } 195 196 // If no store entry, then instruction can issue as soon as the registers 197 // are ready. 198 if (!store_entry) { 199 DPRINTF(MemDepUnit, "No dependency for inst PC " 200 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 201 202 inst_entry->memDepReady = true; 203 204 if (inst->readyToIssue()) { 205 inst_entry->regsReady = true; 206 207 moveToReady(inst_entry); 208 } 209 } else { 210 // Otherwise make the instruction dependent on the store/barrier. 211 DPRINTF(MemDepUnit, "Adding to dependency list; " 212 "inst PC %#x is dependent on [sn:%lli].\n", 213 inst->readPC(), producing_store); 214 215 if (inst->readyToIssue()) { 216 inst_entry->regsReady = true; 217 } 218 219 // Clear the bit saying this instruction can issue. 220 inst->clearCanIssue(); 221 222 // Add this instruction to the list of dependents. 223 store_entry->dependInsts.push_back(inst_entry); 224 225 if (inst->isLoad()) { 226 ++conflictingLoads; 227 } else { 228 ++conflictingStores; 229 } 230 } 231 232 if (inst->isStore()) { 233 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 234 inst->readPC(), inst->seqNum); 235 236 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 237 238 ++insertedStores; 239 } else if (inst->isLoad()) { 240 ++insertedLoads; 241 } else { 242 panic("Unknown type! (most likely a barrier)."); 243 } 244} 245 246template <class MemDepPred, class Impl> 247void 248MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 249{ 250 unsigned tid = inst->threadNumber; 251 252 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 253 254 // Insert the MemDepEntry into the hash. 255 memDepHash.insert( 256 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 257#ifdef DEBUG 258 MemDepEntry::memdep_insert++; 259#endif 260 261 // Add the instruction to the list. 262 instList[tid].push_back(inst); 263 264 inst_entry->listIt = --(instList[tid].end()); 265 266 // Might want to turn this part into an inline function or something. 267 // It's shared between both insert functions. 268 if (inst->isStore()) { 269 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 270 inst->readPC(), inst->seqNum); 271 272 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 273 274 ++insertedStores; 275 } else if (inst->isLoad()) { 276 ++insertedLoads; 277 } else { 278 panic("Unknown type! (most likely a barrier)."); 279 } 280} 281 282template <class MemDepPred, class Impl> 283void 284MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 285{ 286 InstSeqNum barr_sn = barr_inst->seqNum; 287 // Memory barriers block loads and stores, write barriers only stores. 288 if (barr_inst->isMemBarrier()) { 289 loadBarrier = true; 290 loadBarrierSN = barr_sn; 291 storeBarrier = true; 292 storeBarrierSN = barr_sn; 293 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 294 } else if (barr_inst->isWriteBarrier()) { 295 storeBarrier = true; 296 storeBarrierSN = barr_sn; 297 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 298 } 299 300 unsigned tid = barr_inst->threadNumber; 301 302 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 303 304 // Add the MemDepEntry to the hash. 305 memDepHash.insert( 306 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 307#ifdef DEBUG 308 MemDepEntry::memdep_insert++; 309#endif 310 311 // Add the instruction to the instruction list. 312 instList[tid].push_back(barr_inst); 313 314 inst_entry->listIt = --(instList[tid].end()); 315} 316 317template <class MemDepPred, class Impl> 318void 319MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 320{ 321 DPRINTF(MemDepUnit, "Marking registers as ready for " 322 "instruction PC %#x [sn:%lli].\n", 323 inst->readPC(), inst->seqNum); 324 325 MemDepEntryPtr inst_entry = findInHash(inst); 326 327 inst_entry->regsReady = true; 328 329 if (inst_entry->memDepReady) { 330 DPRINTF(MemDepUnit, "Instruction has its memory " 331 "dependencies resolved, adding it to the ready list.\n"); 332 333 moveToReady(inst_entry); 334 } else { 335 DPRINTF(MemDepUnit, "Instruction still waiting on " 336 "memory dependency.\n"); 337 } 338} 339 340template <class MemDepPred, class Impl> 341void 342MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 343{ 344 DPRINTF(MemDepUnit, "Marking non speculative " 345 "instruction PC %#x as ready [sn:%lli].\n", 346 inst->readPC(), inst->seqNum); 347 348 MemDepEntryPtr inst_entry = findInHash(inst); 349 350 moveToReady(inst_entry); 351} 352 353template <class MemDepPred, class Impl> 354void 355MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 356{ 357 instsToReplay.push_back(inst); 358} 359 360template <class MemDepPred, class Impl> 361void 362MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 363{ 364 DynInstPtr temp_inst; 365 366 // For now this replay function replays all waiting memory ops. 367 while (!instsToReplay.empty()) { 368 temp_inst = instsToReplay.front(); 369 370 MemDepEntryPtr inst_entry = findInHash(temp_inst); 371 372 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 373 "[sn:%lli].\n", 374 temp_inst->readPC(), temp_inst->seqNum); 375 376 moveToReady(inst_entry); 377 378 instsToReplay.pop_front(); 379 } 380} 381 382template <class MemDepPred, class Impl> 383void 384MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 385{ 386 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 387 "[sn:%lli].\n", 388 inst->readPC(), inst->seqNum); 389 390 unsigned tid = inst->threadNumber; 391 392 // Remove the instruction from the hash and the list. 393 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 394 395 assert(hash_it != memDepHash.end()); 396 397 instList[tid].erase((*hash_it).second->listIt); 398 399 (*hash_it).second = NULL; 400 401 memDepHash.erase(hash_it); 402#ifdef DEBUG 403 MemDepEntry::memdep_erase++; 404#endif 405} 406 407template <class MemDepPred, class Impl> 408void 409MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 410{ 411 wakeDependents(inst); 412 completed(inst); 413 414 InstSeqNum barr_sn = inst->seqNum; 415 416 if (inst->isMemBarrier()) { 417 assert(loadBarrier && storeBarrier); 418 if (loadBarrierSN == barr_sn) 419 loadBarrier = false; 420 if (storeBarrierSN == barr_sn) 421 storeBarrier = false; 422 } else if (inst->isWriteBarrier()) { 423 assert(storeBarrier); 424 if (storeBarrierSN == barr_sn) 425 storeBarrier = false; 426 } 427} 428 429template <class MemDepPred, class Impl> 430void 431MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 432{ 433 // Only stores and barriers have dependents. 434 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 435 return; 436 } 437 438 MemDepEntryPtr inst_entry = findInHash(inst); 439 440 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 441 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 442 443 if (!woken_inst->inst) { 444 // Potentially removed mem dep entries could be on this list 445 continue; 446 } 447 448 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 449 "[sn:%lli].\n", 450 woken_inst->inst->seqNum); 451 452 if (woken_inst->regsReady && !woken_inst->squashed) { 453 moveToReady(woken_inst); 454 } else { 455 woken_inst->memDepReady = true; 456 } 457 } 458 459 inst_entry->dependInsts.clear(); 460} 461 462template <class MemDepPred, class Impl> 463void 464MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 465 unsigned tid) 466{ 467 if (!instsToReplay.empty()) { 468 ListIt replay_it = instsToReplay.begin(); 469 while (replay_it != instsToReplay.end()) { 470 if ((*replay_it)->threadNumber == tid && 471 (*replay_it)->seqNum > squashed_num) { 472 instsToReplay.erase(replay_it++); 473 } else { 474 ++replay_it; 475 } 476 } 477 } 478 479 ListIt squash_it = instList[tid].end(); 480 --squash_it; 481 482 MemDepHashIt hash_it; 483 484 while (!instList[tid].empty() && 485 (*squash_it)->seqNum > squashed_num) { 486 487 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 488 (*squash_it)->seqNum); 489 490 hash_it = memDepHash.find((*squash_it)->seqNum); 491 492 assert(hash_it != memDepHash.end()); 493 494 (*hash_it).second->squashed = true; 495 496 (*hash_it).second = NULL; 497 498 memDepHash.erase(hash_it); 499#ifdef DEBUG 500 MemDepEntry::memdep_erase++; 501#endif 502 503 instList[tid].erase(squash_it--); 504 } 505 506 // Tell the dependency predictor to squash as well. 507 depPred.squash(squashed_num, tid); 508} 509 510template <class MemDepPred, class Impl> 511void 512MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 513 DynInstPtr &violating_load) 514{ 515 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 516 " load: %#x, store: %#x\n", violating_load->readPC(), 517 store_inst->readPC()); 518 // Tell the memory dependence unit of the violation. 519 depPred.violation(violating_load->readPC(), store_inst->readPC()); 520} 521 522template <class MemDepPred, class Impl> 523void 524MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 525{ 526 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 527 inst->readPC(), inst->seqNum); 528 529 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 530} 531 532template <class MemDepPred, class Impl> 533inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 534MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 535{ 536 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 537 538 assert(hash_it != memDepHash.end()); 539 540 return (*hash_it).second; 541} 542 543template <class MemDepPred, class Impl> 544inline void 545MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 546{ 547 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 548 "to the ready list.\n", woken_inst_entry->inst->seqNum); 549 550 assert(!woken_inst_entry->squashed); 551 552 iqPtr->addReadyMemInst(woken_inst_entry->inst); 553} 554 555 556template <class MemDepPred, class Impl> 557void 558MemDepUnit<MemDepPred, Impl>::dumpLists() 559{ 560 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 561 cprintf("Instruction list %i size: %i\n", 562 tid, instList[tid].size()); 563 564 ListIt inst_list_it = instList[tid].begin(); 565 int num = 0; 566 567 while (inst_list_it != instList[tid].end()) { 568 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 569 "Squashed:%i\n\n", 570 num, (*inst_list_it)->readPC(), 571 (*inst_list_it)->seqNum, 572 (*inst_list_it)->threadNumber, 573 (*inst_list_it)->isIssued(), 574 (*inst_list_it)->isSquashed()); 575 inst_list_it++; 576 ++num; 577 } 578 } 579 580 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 581 582#ifdef DEBUG 583 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 584#endif 585}
| 109 .desc("Number of conflicting stores."); 110} 111 112template <class MemDepPred, class Impl> 113void 114MemDepUnit<MemDepPred, Impl>::switchOut() 115{ 116 assert(instList[0].empty()); 117 assert(instsToReplay.empty()); 118 assert(memDepHash.empty()); 119 // Clear any state. 120 for (int i = 0; i < Impl::MaxThreads; ++i) { 121 instList[i].clear(); 122 } 123 instsToReplay.clear(); 124 memDepHash.clear(); 125} 126 127template <class MemDepPred, class Impl> 128void 129MemDepUnit<MemDepPred, Impl>::takeOverFrom() 130{ 131 // Be sure to reset all state. 132 loadBarrier = storeBarrier = false; 133 loadBarrierSN = storeBarrierSN = 0; 134 depPred.clear(); 135} 136 137template <class MemDepPred, class Impl> 138void 139MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 140{ 141 iqPtr = iq_ptr; 142} 143 144template <class MemDepPred, class Impl> 145void 146MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 147{ 148 unsigned tid = inst->threadNumber; 149 150 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 151 152 // Add the MemDepEntry to the hash. 153 memDepHash.insert( 154 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 155#ifdef DEBUG 156 MemDepEntry::memdep_insert++; 157#endif 158 159 instList[tid].push_back(inst); 160 161 inst_entry->listIt = --(instList[tid].end()); 162 163 // Check any barriers and the dependence predictor for any 164 // producing memrefs/stores. 165 InstSeqNum producing_store; 166 if (inst->isLoad() && loadBarrier) { 167 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 168 loadBarrierSN); 169 producing_store = loadBarrierSN; 170 } else if (inst->isStore() && storeBarrier) { 171 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 172 storeBarrierSN); 173 producing_store = storeBarrierSN; 174 } else { 175 producing_store = depPred.checkInst(inst->readPC()); 176 } 177 178 MemDepEntryPtr store_entry = NULL; 179 180 // If there is a producing store, try to find the entry. 181 if (producing_store != 0) { 182 DPRINTF(MemDepUnit, "Searching for producer\n"); 183 MemDepHashIt hash_it = memDepHash.find(producing_store); 184 185 if (hash_it != memDepHash.end()) { 186 store_entry = (*hash_it).second; 187 DPRINTF(MemDepUnit, "Proucer found\n"); 188 } 189 } 190 191 // If no store entry, then instruction can issue as soon as the registers 192 // are ready. 193 if (!store_entry) { 194 DPRINTF(MemDepUnit, "No dependency for inst PC " 195 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 196 197 inst_entry->memDepReady = true; 198 199 if (inst->readyToIssue()) { 200 inst_entry->regsReady = true; 201 202 moveToReady(inst_entry); 203 } 204 } else { 205 // Otherwise make the instruction dependent on the store/barrier. 206 DPRINTF(MemDepUnit, "Adding to dependency list; " 207 "inst PC %#x is dependent on [sn:%lli].\n", 208 inst->readPC(), producing_store); 209 210 if (inst->readyToIssue()) { 211 inst_entry->regsReady = true; 212 } 213 214 // Clear the bit saying this instruction can issue. 215 inst->clearCanIssue(); 216 217 // Add this instruction to the list of dependents. 218 store_entry->dependInsts.push_back(inst_entry); 219 220 if (inst->isLoad()) { 221 ++conflictingLoads; 222 } else { 223 ++conflictingStores; 224 } 225 } 226 227 if (inst->isStore()) { 228 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 229 inst->readPC(), inst->seqNum); 230 231 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 232 233 ++insertedStores; 234 } else if (inst->isLoad()) { 235 ++insertedLoads; 236 } else { 237 panic("Unknown type! (most likely a barrier)."); 238 } 239} 240 241template <class MemDepPred, class Impl> 242void 243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 244{ 245 unsigned tid = inst->threadNumber; 246 247 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 248 249 // Insert the MemDepEntry into the hash. 250 memDepHash.insert( 251 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 252#ifdef DEBUG 253 MemDepEntry::memdep_insert++; 254#endif 255 256 // Add the instruction to the list. 257 instList[tid].push_back(inst); 258 259 inst_entry->listIt = --(instList[tid].end()); 260 261 // Might want to turn this part into an inline function or something. 262 // It's shared between both insert functions. 263 if (inst->isStore()) { 264 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 265 inst->readPC(), inst->seqNum); 266 267 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 268 269 ++insertedStores; 270 } else if (inst->isLoad()) { 271 ++insertedLoads; 272 } else { 273 panic("Unknown type! (most likely a barrier)."); 274 } 275} 276 277template <class MemDepPred, class Impl> 278void 279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 280{ 281 InstSeqNum barr_sn = barr_inst->seqNum; 282 // Memory barriers block loads and stores, write barriers only stores. 283 if (barr_inst->isMemBarrier()) { 284 loadBarrier = true; 285 loadBarrierSN = barr_sn; 286 storeBarrier = true; 287 storeBarrierSN = barr_sn; 288 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 289 } else if (barr_inst->isWriteBarrier()) { 290 storeBarrier = true; 291 storeBarrierSN = barr_sn; 292 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 293 } 294 295 unsigned tid = barr_inst->threadNumber; 296 297 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 298 299 // Add the MemDepEntry to the hash. 300 memDepHash.insert( 301 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 302#ifdef DEBUG 303 MemDepEntry::memdep_insert++; 304#endif 305 306 // Add the instruction to the instruction list. 307 instList[tid].push_back(barr_inst); 308 309 inst_entry->listIt = --(instList[tid].end()); 310} 311 312template <class MemDepPred, class Impl> 313void 314MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 315{ 316 DPRINTF(MemDepUnit, "Marking registers as ready for " 317 "instruction PC %#x [sn:%lli].\n", 318 inst->readPC(), inst->seqNum); 319 320 MemDepEntryPtr inst_entry = findInHash(inst); 321 322 inst_entry->regsReady = true; 323 324 if (inst_entry->memDepReady) { 325 DPRINTF(MemDepUnit, "Instruction has its memory " 326 "dependencies resolved, adding it to the ready list.\n"); 327 328 moveToReady(inst_entry); 329 } else { 330 DPRINTF(MemDepUnit, "Instruction still waiting on " 331 "memory dependency.\n"); 332 } 333} 334 335template <class MemDepPred, class Impl> 336void 337MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 338{ 339 DPRINTF(MemDepUnit, "Marking non speculative " 340 "instruction PC %#x as ready [sn:%lli].\n", 341 inst->readPC(), inst->seqNum); 342 343 MemDepEntryPtr inst_entry = findInHash(inst); 344 345 moveToReady(inst_entry); 346} 347 348template <class MemDepPred, class Impl> 349void 350MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 351{ 352 instsToReplay.push_back(inst); 353} 354 355template <class MemDepPred, class Impl> 356void 357MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 358{ 359 DynInstPtr temp_inst; 360 361 // For now this replay function replays all waiting memory ops. 362 while (!instsToReplay.empty()) { 363 temp_inst = instsToReplay.front(); 364 365 MemDepEntryPtr inst_entry = findInHash(temp_inst); 366 367 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 368 "[sn:%lli].\n", 369 temp_inst->readPC(), temp_inst->seqNum); 370 371 moveToReady(inst_entry); 372 373 instsToReplay.pop_front(); 374 } 375} 376 377template <class MemDepPred, class Impl> 378void 379MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 380{ 381 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 382 "[sn:%lli].\n", 383 inst->readPC(), inst->seqNum); 384 385 unsigned tid = inst->threadNumber; 386 387 // Remove the instruction from the hash and the list. 388 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 389 390 assert(hash_it != memDepHash.end()); 391 392 instList[tid].erase((*hash_it).second->listIt); 393 394 (*hash_it).second = NULL; 395 396 memDepHash.erase(hash_it); 397#ifdef DEBUG 398 MemDepEntry::memdep_erase++; 399#endif 400} 401 402template <class MemDepPred, class Impl> 403void 404MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 405{ 406 wakeDependents(inst); 407 completed(inst); 408 409 InstSeqNum barr_sn = inst->seqNum; 410 411 if (inst->isMemBarrier()) { 412 assert(loadBarrier && storeBarrier); 413 if (loadBarrierSN == barr_sn) 414 loadBarrier = false; 415 if (storeBarrierSN == barr_sn) 416 storeBarrier = false; 417 } else if (inst->isWriteBarrier()) { 418 assert(storeBarrier); 419 if (storeBarrierSN == barr_sn) 420 storeBarrier = false; 421 } 422} 423 424template <class MemDepPred, class Impl> 425void 426MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 427{ 428 // Only stores and barriers have dependents. 429 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 430 return; 431 } 432 433 MemDepEntryPtr inst_entry = findInHash(inst); 434 435 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 436 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 437 438 if (!woken_inst->inst) { 439 // Potentially removed mem dep entries could be on this list 440 continue; 441 } 442 443 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 444 "[sn:%lli].\n", 445 woken_inst->inst->seqNum); 446 447 if (woken_inst->regsReady && !woken_inst->squashed) { 448 moveToReady(woken_inst); 449 } else { 450 woken_inst->memDepReady = true; 451 } 452 } 453 454 inst_entry->dependInsts.clear(); 455} 456 457template <class MemDepPred, class Impl> 458void 459MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 460 unsigned tid) 461{ 462 if (!instsToReplay.empty()) { 463 ListIt replay_it = instsToReplay.begin(); 464 while (replay_it != instsToReplay.end()) { 465 if ((*replay_it)->threadNumber == tid && 466 (*replay_it)->seqNum > squashed_num) { 467 instsToReplay.erase(replay_it++); 468 } else { 469 ++replay_it; 470 } 471 } 472 } 473 474 ListIt squash_it = instList[tid].end(); 475 --squash_it; 476 477 MemDepHashIt hash_it; 478 479 while (!instList[tid].empty() && 480 (*squash_it)->seqNum > squashed_num) { 481 482 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 483 (*squash_it)->seqNum); 484 485 hash_it = memDepHash.find((*squash_it)->seqNum); 486 487 assert(hash_it != memDepHash.end()); 488 489 (*hash_it).second->squashed = true; 490 491 (*hash_it).second = NULL; 492 493 memDepHash.erase(hash_it); 494#ifdef DEBUG 495 MemDepEntry::memdep_erase++; 496#endif 497 498 instList[tid].erase(squash_it--); 499 } 500 501 // Tell the dependency predictor to squash as well. 502 depPred.squash(squashed_num, tid); 503} 504 505template <class MemDepPred, class Impl> 506void 507MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 508 DynInstPtr &violating_load) 509{ 510 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 511 " load: %#x, store: %#x\n", violating_load->readPC(), 512 store_inst->readPC()); 513 // Tell the memory dependence unit of the violation. 514 depPred.violation(violating_load->readPC(), store_inst->readPC()); 515} 516 517template <class MemDepPred, class Impl> 518void 519MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 520{ 521 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 522 inst->readPC(), inst->seqNum); 523 524 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 525} 526 527template <class MemDepPred, class Impl> 528inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 529MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 530{ 531 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 532 533 assert(hash_it != memDepHash.end()); 534 535 return (*hash_it).second; 536} 537 538template <class MemDepPred, class Impl> 539inline void 540MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 541{ 542 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 543 "to the ready list.\n", woken_inst_entry->inst->seqNum); 544 545 assert(!woken_inst_entry->squashed); 546 547 iqPtr->addReadyMemInst(woken_inst_entry->inst); 548} 549 550 551template <class MemDepPred, class Impl> 552void 553MemDepUnit<MemDepPred, Impl>::dumpLists() 554{ 555 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 556 cprintf("Instruction list %i size: %i\n", 557 tid, instList[tid].size()); 558 559 ListIt inst_list_it = instList[tid].begin(); 560 int num = 0; 561 562 while (inst_list_it != instList[tid].end()) { 563 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 564 "Squashed:%i\n\n", 565 num, (*inst_list_it)->readPC(), 566 (*inst_list_it)->seqNum, 567 (*inst_list_it)->threadNumber, 568 (*inst_list_it)->isIssued(), 569 (*inst_list_it)->isSquashed()); 570 inst_list_it++; 571 ++num; 572 } 573 } 574 575 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 576 577#ifdef DEBUG 578 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 579#endif 580}
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