1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35
36template <class MemDepPred, class Impl>
37MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
38 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
39 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
40{
41 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
42}
43
44template <class MemDepPred, class Impl>
45MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
46{
47 for (int tid=0; tid < Impl::MaxThreads; tid++) {
48
49 ListIt inst_list_it = instList[tid].begin();
50
51 MemDepHashIt hash_it;
52
53 while (!instList[tid].empty()) {
54 hash_it = memDepHash.find((*inst_list_it)->seqNum);
55
56 assert(hash_it != memDepHash.end());
57
58 memDepHash.erase(hash_it);
59
60 instList[tid].erase(inst_list_it++);
61 }
62 }
63
64#ifdef DEBUG
65 assert(MemDepEntry::memdep_count == 0);
66#endif
67}
68
69template <class MemDepPred, class Impl>
70std::string
71MemDepUnit<MemDepPred, Impl>::name() const
72{
73 return "memdepunit";
74}
75
76template <class MemDepPred, class Impl>
77void
78MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
79{
80 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
81
82 id = tid;
83
84 depPred.init(params->SSITSize, params->LFSTSize);
85}
86
87template <class MemDepPred, class Impl>
88void
89MemDepUnit<MemDepPred, Impl>::regStats()
90{
91 insertedLoads
92 .name(name() + ".memDep.insertedLoads")
93 .desc("Number of loads inserted to the mem dependence unit.");
94
95 insertedStores
96 .name(name() + ".memDep.insertedStores")
97 .desc("Number of stores inserted to the mem dependence unit.");
98
99 conflictingLoads
100 .name(name() + ".memDep.conflictingLoads")
101 .desc("Number of conflicting loads.");
102
103 conflictingStores
104 .name(name() + ".memDep.conflictingStores")
105 .desc("Number of conflicting stores.");
106}
107
108template <class MemDepPred, class Impl>
109void
110MemDepUnit<MemDepPred, Impl>::switchOut()
111{
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35
36template <class MemDepPred, class Impl>
37MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
38 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
39 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
40{
41 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
42}
43
44template <class MemDepPred, class Impl>
45MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
46{
47 for (int tid=0; tid < Impl::MaxThreads; tid++) {
48
49 ListIt inst_list_it = instList[tid].begin();
50
51 MemDepHashIt hash_it;
52
53 while (!instList[tid].empty()) {
54 hash_it = memDepHash.find((*inst_list_it)->seqNum);
55
56 assert(hash_it != memDepHash.end());
57
58 memDepHash.erase(hash_it);
59
60 instList[tid].erase(inst_list_it++);
61 }
62 }
63
64#ifdef DEBUG
65 assert(MemDepEntry::memdep_count == 0);
66#endif
67}
68
69template <class MemDepPred, class Impl>
70std::string
71MemDepUnit<MemDepPred, Impl>::name() const
72{
73 return "memdepunit";
74}
75
76template <class MemDepPred, class Impl>
77void
78MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
79{
80 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
81
82 id = tid;
83
84 depPred.init(params->SSITSize, params->LFSTSize);
85}
86
87template <class MemDepPred, class Impl>
88void
89MemDepUnit<MemDepPred, Impl>::regStats()
90{
91 insertedLoads
92 .name(name() + ".memDep.insertedLoads")
93 .desc("Number of loads inserted to the mem dependence unit.");
94
95 insertedStores
96 .name(name() + ".memDep.insertedStores")
97 .desc("Number of stores inserted to the mem dependence unit.");
98
99 conflictingLoads
100 .name(name() + ".memDep.conflictingLoads")
101 .desc("Number of conflicting loads.");
102
103 conflictingStores
104 .name(name() + ".memDep.conflictingStores")
105 .desc("Number of conflicting stores.");
106}
107
108template <class MemDepPred, class Impl>
109void
110MemDepUnit<MemDepPred, Impl>::switchOut()
111{
|
112 // Clear any state.
113 for (int i = 0; i < Impl::MaxThreads; ++i) {
114 instList[i].clear();
115 }
116 instsToReplay.clear();
117 memDepHash.clear();
118}
119
120template <class MemDepPred, class Impl>
121void
122MemDepUnit<MemDepPred, Impl>::takeOverFrom()
123{
124 // Be sure to reset all state.
125 loadBarrier = storeBarrier = false;
126 loadBarrierSN = storeBarrierSN = 0;
127 depPred.clear();
128}
129
130template <class MemDepPred, class Impl>
131void
132MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
133{
134 iqPtr = iq_ptr;
135}
136
137template <class MemDepPred, class Impl>
138void
139MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
140{
141 unsigned tid = inst->threadNumber;
142
143 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
144
145 // Add the MemDepEntry to the hash.
146 memDepHash.insert(
147 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
148#ifdef DEBUG
149 MemDepEntry::memdep_insert++;
150#endif
151
152 instList[tid].push_back(inst);
153
154 inst_entry->listIt = --(instList[tid].end());
155
156 // Check any barriers and the dependence predictor for any
157 // producing memrefs/stores.
158 InstSeqNum producing_store;
159 if (inst->isLoad() && loadBarrier) {
160 producing_store = loadBarrierSN;
161 } else if (inst->isStore() && storeBarrier) {
162 producing_store = storeBarrierSN;
163 } else {
164 producing_store = depPred.checkInst(inst->readPC());
165 }
166
167 MemDepEntryPtr store_entry = NULL;
168
169 // If there is a producing store, try to find the entry.
170 if (producing_store != 0) {
171 MemDepHashIt hash_it = memDepHash.find(producing_store);
172
173 if (hash_it != memDepHash.end()) {
174 store_entry = (*hash_it).second;
175 }
176 }
177
178 // If no store entry, then instruction can issue as soon as the registers
179 // are ready.
180 if (!store_entry) {
181 DPRINTF(MemDepUnit, "No dependency for inst PC "
182 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
183
184 inst_entry->memDepReady = true;
185
186 if (inst->readyToIssue()) {
187 inst_entry->regsReady = true;
188
189 moveToReady(inst_entry);
190 }
191 } else {
192 // Otherwise make the instruction dependent on the store/barrier.
193 DPRINTF(MemDepUnit, "Adding to dependency list; "
194 "inst PC %#x is dependent on [sn:%lli].\n",
195 inst->readPC(), producing_store);
196
197 if (inst->readyToIssue()) {
198 inst_entry->regsReady = true;
199 }
200
201 // Add this instruction to the list of dependents.
202 store_entry->dependInsts.push_back(inst_entry);
203
204 if (inst->isLoad()) {
205 ++conflictingLoads;
206 } else {
207 ++conflictingStores;
208 }
209 }
210
211 if (inst->isStore()) {
212 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
213 inst->readPC(), inst->seqNum);
214
215 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
216
217 ++insertedStores;
218 } else if (inst->isLoad()) {
219 ++insertedLoads;
220 } else {
221 panic("Unknown type! (most likely a barrier).");
222 }
223}
224
225template <class MemDepPred, class Impl>
226void
227MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
228{
229 unsigned tid = inst->threadNumber;
230
231 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
232
233 // Insert the MemDepEntry into the hash.
234 memDepHash.insert(
235 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
236#ifdef DEBUG
237 MemDepEntry::memdep_insert++;
238#endif
239
240 // Add the instruction to the list.
241 instList[tid].push_back(inst);
242
243 inst_entry->listIt = --(instList[tid].end());
244
245 // Might want to turn this part into an inline function or something.
246 // It's shared between both insert functions.
247 if (inst->isStore()) {
248 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
249 inst->readPC(), inst->seqNum);
250
251 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
252
253 ++insertedStores;
254 } else if (inst->isLoad()) {
255 ++insertedLoads;
256 } else {
257 panic("Unknown type! (most likely a barrier).");
258 }
259}
260
261template <class MemDepPred, class Impl>
262void
263MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
264{
265 InstSeqNum barr_sn = barr_inst->seqNum;
266 // Memory barriers block loads and stores, write barriers only stores.
267 if (barr_inst->isMemBarrier()) {
268 loadBarrier = true;
269 loadBarrierSN = barr_sn;
270 storeBarrier = true;
271 storeBarrierSN = barr_sn;
272 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
273 } else if (barr_inst->isWriteBarrier()) {
274 storeBarrier = true;
275 storeBarrierSN = barr_sn;
276 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
277 }
278
279 unsigned tid = barr_inst->threadNumber;
280
281 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
282
283 // Add the MemDepEntry to the hash.
284 memDepHash.insert(
285 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
286#ifdef DEBUG
287 MemDepEntry::memdep_insert++;
288#endif
289
290 // Add the instruction to the instruction list.
291 instList[tid].push_back(barr_inst);
292
293 inst_entry->listIt = --(instList[tid].end());
294}
295
296template <class MemDepPred, class Impl>
297void
298MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
299{
300 DPRINTF(MemDepUnit, "Marking registers as ready for "
301 "instruction PC %#x [sn:%lli].\n",
302 inst->readPC(), inst->seqNum);
303
304 MemDepEntryPtr inst_entry = findInHash(inst);
305
306 inst_entry->regsReady = true;
307
308 if (inst_entry->memDepReady) {
309 DPRINTF(MemDepUnit, "Instruction has its memory "
310 "dependencies resolved, adding it to the ready list.\n");
311
312 moveToReady(inst_entry);
313 } else {
314 DPRINTF(MemDepUnit, "Instruction still waiting on "
315 "memory dependency.\n");
316 }
317}
318
319template <class MemDepPred, class Impl>
320void
321MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
322{
323 DPRINTF(MemDepUnit, "Marking non speculative "
324 "instruction PC %#x as ready [sn:%lli].\n",
325 inst->readPC(), inst->seqNum);
326
327 MemDepEntryPtr inst_entry = findInHash(inst);
328
329 moveToReady(inst_entry);
330}
331
332template <class MemDepPred, class Impl>
333void
334MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
335{
336 instsToReplay.push_back(inst);
337}
338
339template <class MemDepPred, class Impl>
340void
341MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
342{
343 DynInstPtr temp_inst;
344 bool found_inst = false;
345
346 // For now this replay function replays all waiting memory ops.
347 while (!instsToReplay.empty()) {
348 temp_inst = instsToReplay.front();
349
350 MemDepEntryPtr inst_entry = findInHash(temp_inst);
351
352 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
353 "[sn:%lli].\n",
354 temp_inst->readPC(), temp_inst->seqNum);
355
356 moveToReady(inst_entry);
357
358 if (temp_inst == inst) {
359 found_inst = true;
360 }
361
362 instsToReplay.pop_front();
363 }
364
365 assert(found_inst);
366}
367
368template <class MemDepPred, class Impl>
369void
370MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
371{
372 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
373 "[sn:%lli].\n",
374 inst->readPC(), inst->seqNum);
375
376 unsigned tid = inst->threadNumber;
377
378 // Remove the instruction from the hash and the list.
379 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
380
381 assert(hash_it != memDepHash.end());
382
383 instList[tid].erase((*hash_it).second->listIt);
384
385 (*hash_it).second = NULL;
386
387 memDepHash.erase(hash_it);
388#ifdef DEBUG
389 MemDepEntry::memdep_erase++;
390#endif
391}
392
393template <class MemDepPred, class Impl>
394void
395MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
396{
397 wakeDependents(inst);
398 completed(inst);
399
400 InstSeqNum barr_sn = inst->seqNum;
401
402 if (inst->isMemBarrier()) {
403 assert(loadBarrier && storeBarrier);
404 if (loadBarrierSN == barr_sn)
405 loadBarrier = false;
406 if (storeBarrierSN == barr_sn)
407 storeBarrier = false;
408 } else if (inst->isWriteBarrier()) {
409 assert(storeBarrier);
410 if (storeBarrierSN == barr_sn)
411 storeBarrier = false;
412 }
413}
414
415template <class MemDepPred, class Impl>
416void
417MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
418{
419 // Only stores and barriers have dependents.
420 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
421 return;
422 }
423
424 MemDepEntryPtr inst_entry = findInHash(inst);
425
426 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
427 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
428
429 if (!woken_inst->inst) {
430 // Potentially removed mem dep entries could be on this list
431 continue;
432 }
433
434 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
435 "[sn:%lli].\n",
436 woken_inst->inst->seqNum);
437
438 if (woken_inst->regsReady && !woken_inst->squashed) {
439 moveToReady(woken_inst);
440 } else {
441 woken_inst->memDepReady = true;
442 }
443 }
444
445 inst_entry->dependInsts.clear();
446}
447
448template <class MemDepPred, class Impl>
449void
450MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
451 unsigned tid)
452{
453 if (!instsToReplay.empty()) {
454 ListIt replay_it = instsToReplay.begin();
455 while (replay_it != instsToReplay.end()) {
456 if ((*replay_it)->threadNumber == tid &&
457 (*replay_it)->seqNum > squashed_num) {
458 instsToReplay.erase(replay_it++);
459 } else {
460 ++replay_it;
461 }
462 }
463 }
464
465 ListIt squash_it = instList[tid].end();
466 --squash_it;
467
468 MemDepHashIt hash_it;
469
470 while (!instList[tid].empty() &&
471 (*squash_it)->seqNum > squashed_num) {
472
473 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
474 (*squash_it)->seqNum);
475
476 hash_it = memDepHash.find((*squash_it)->seqNum);
477
478 assert(hash_it != memDepHash.end());
479
480 (*hash_it).second->squashed = true;
481
482 (*hash_it).second = NULL;
483
484 memDepHash.erase(hash_it);
485#ifdef DEBUG
486 MemDepEntry::memdep_erase++;
487#endif
488
489 instList[tid].erase(squash_it--);
490 }
491
492 // Tell the dependency predictor to squash as well.
493 depPred.squash(squashed_num, tid);
494}
495
496template <class MemDepPred, class Impl>
497void
498MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
499 DynInstPtr &violating_load)
500{
501 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
502 " load: %#x, store: %#x\n", violating_load->readPC(),
503 store_inst->readPC());
504 // Tell the memory dependence unit of the violation.
505 depPred.violation(violating_load->readPC(), store_inst->readPC());
506}
507
508template <class MemDepPred, class Impl>
509void
510MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
511{
512 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
513 inst->readPC(), inst->seqNum);
514
515 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
516}
517
518template <class MemDepPred, class Impl>
519inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
520MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
521{
522 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
523
524 assert(hash_it != memDepHash.end());
525
526 return (*hash_it).second;
527}
528
529template <class MemDepPred, class Impl>
530inline void
531MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
532{
533 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
534 "to the ready list.\n", woken_inst_entry->inst->seqNum);
535
536 assert(!woken_inst_entry->squashed);
537
538 iqPtr->addReadyMemInst(woken_inst_entry->inst);
539}
540
541
542template <class MemDepPred, class Impl>
543void
544MemDepUnit<MemDepPred, Impl>::dumpLists()
545{
546 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
547 cprintf("Instruction list %i size: %i\n",
548 tid, instList[tid].size());
549
550 ListIt inst_list_it = instList[tid].begin();
551 int num = 0;
552
553 while (inst_list_it != instList[tid].end()) {
554 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
555 "Squashed:%i\n\n",
556 num, (*inst_list_it)->readPC(),
557 (*inst_list_it)->seqNum,
558 (*inst_list_it)->threadNumber,
559 (*inst_list_it)->isIssued(),
560 (*inst_list_it)->isSquashed());
561 inst_list_it++;
562 ++num;
563 }
564 }
565
566 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
567
568#ifdef DEBUG
569 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
570#endif
571}
| 115 // Clear any state.
116 for (int i = 0; i < Impl::MaxThreads; ++i) {
117 instList[i].clear();
118 }
119 instsToReplay.clear();
120 memDepHash.clear();
121}
122
123template <class MemDepPred, class Impl>
124void
125MemDepUnit<MemDepPred, Impl>::takeOverFrom()
126{
127 // Be sure to reset all state.
128 loadBarrier = storeBarrier = false;
129 loadBarrierSN = storeBarrierSN = 0;
130 depPred.clear();
131}
132
133template <class MemDepPred, class Impl>
134void
135MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
136{
137 iqPtr = iq_ptr;
138}
139
140template <class MemDepPred, class Impl>
141void
142MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
143{
144 unsigned tid = inst->threadNumber;
145
146 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
147
148 // Add the MemDepEntry to the hash.
149 memDepHash.insert(
150 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
151#ifdef DEBUG
152 MemDepEntry::memdep_insert++;
153#endif
154
155 instList[tid].push_back(inst);
156
157 inst_entry->listIt = --(instList[tid].end());
158
159 // Check any barriers and the dependence predictor for any
160 // producing memrefs/stores.
161 InstSeqNum producing_store;
162 if (inst->isLoad() && loadBarrier) {
163 producing_store = loadBarrierSN;
164 } else if (inst->isStore() && storeBarrier) {
165 producing_store = storeBarrierSN;
166 } else {
167 producing_store = depPred.checkInst(inst->readPC());
168 }
169
170 MemDepEntryPtr store_entry = NULL;
171
172 // If there is a producing store, try to find the entry.
173 if (producing_store != 0) {
174 MemDepHashIt hash_it = memDepHash.find(producing_store);
175
176 if (hash_it != memDepHash.end()) {
177 store_entry = (*hash_it).second;
178 }
179 }
180
181 // If no store entry, then instruction can issue as soon as the registers
182 // are ready.
183 if (!store_entry) {
184 DPRINTF(MemDepUnit, "No dependency for inst PC "
185 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
186
187 inst_entry->memDepReady = true;
188
189 if (inst->readyToIssue()) {
190 inst_entry->regsReady = true;
191
192 moveToReady(inst_entry);
193 }
194 } else {
195 // Otherwise make the instruction dependent on the store/barrier.
196 DPRINTF(MemDepUnit, "Adding to dependency list; "
197 "inst PC %#x is dependent on [sn:%lli].\n",
198 inst->readPC(), producing_store);
199
200 if (inst->readyToIssue()) {
201 inst_entry->regsReady = true;
202 }
203
204 // Add this instruction to the list of dependents.
205 store_entry->dependInsts.push_back(inst_entry);
206
207 if (inst->isLoad()) {
208 ++conflictingLoads;
209 } else {
210 ++conflictingStores;
211 }
212 }
213
214 if (inst->isStore()) {
215 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
216 inst->readPC(), inst->seqNum);
217
218 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
219
220 ++insertedStores;
221 } else if (inst->isLoad()) {
222 ++insertedLoads;
223 } else {
224 panic("Unknown type! (most likely a barrier).");
225 }
226}
227
228template <class MemDepPred, class Impl>
229void
230MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
231{
232 unsigned tid = inst->threadNumber;
233
234 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
235
236 // Insert the MemDepEntry into the hash.
237 memDepHash.insert(
238 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
239#ifdef DEBUG
240 MemDepEntry::memdep_insert++;
241#endif
242
243 // Add the instruction to the list.
244 instList[tid].push_back(inst);
245
246 inst_entry->listIt = --(instList[tid].end());
247
248 // Might want to turn this part into an inline function or something.
249 // It's shared between both insert functions.
250 if (inst->isStore()) {
251 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
252 inst->readPC(), inst->seqNum);
253
254 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
255
256 ++insertedStores;
257 } else if (inst->isLoad()) {
258 ++insertedLoads;
259 } else {
260 panic("Unknown type! (most likely a barrier).");
261 }
262}
263
264template <class MemDepPred, class Impl>
265void
266MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
267{
268 InstSeqNum barr_sn = barr_inst->seqNum;
269 // Memory barriers block loads and stores, write barriers only stores.
270 if (barr_inst->isMemBarrier()) {
271 loadBarrier = true;
272 loadBarrierSN = barr_sn;
273 storeBarrier = true;
274 storeBarrierSN = barr_sn;
275 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
276 } else if (barr_inst->isWriteBarrier()) {
277 storeBarrier = true;
278 storeBarrierSN = barr_sn;
279 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
280 }
281
282 unsigned tid = barr_inst->threadNumber;
283
284 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
285
286 // Add the MemDepEntry to the hash.
287 memDepHash.insert(
288 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
289#ifdef DEBUG
290 MemDepEntry::memdep_insert++;
291#endif
292
293 // Add the instruction to the instruction list.
294 instList[tid].push_back(barr_inst);
295
296 inst_entry->listIt = --(instList[tid].end());
297}
298
299template <class MemDepPred, class Impl>
300void
301MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
302{
303 DPRINTF(MemDepUnit, "Marking registers as ready for "
304 "instruction PC %#x [sn:%lli].\n",
305 inst->readPC(), inst->seqNum);
306
307 MemDepEntryPtr inst_entry = findInHash(inst);
308
309 inst_entry->regsReady = true;
310
311 if (inst_entry->memDepReady) {
312 DPRINTF(MemDepUnit, "Instruction has its memory "
313 "dependencies resolved, adding it to the ready list.\n");
314
315 moveToReady(inst_entry);
316 } else {
317 DPRINTF(MemDepUnit, "Instruction still waiting on "
318 "memory dependency.\n");
319 }
320}
321
322template <class MemDepPred, class Impl>
323void
324MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
325{
326 DPRINTF(MemDepUnit, "Marking non speculative "
327 "instruction PC %#x as ready [sn:%lli].\n",
328 inst->readPC(), inst->seqNum);
329
330 MemDepEntryPtr inst_entry = findInHash(inst);
331
332 moveToReady(inst_entry);
333}
334
335template <class MemDepPred, class Impl>
336void
337MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
338{
339 instsToReplay.push_back(inst);
340}
341
342template <class MemDepPred, class Impl>
343void
344MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
345{
346 DynInstPtr temp_inst;
347 bool found_inst = false;
348
349 // For now this replay function replays all waiting memory ops.
350 while (!instsToReplay.empty()) {
351 temp_inst = instsToReplay.front();
352
353 MemDepEntryPtr inst_entry = findInHash(temp_inst);
354
355 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
356 "[sn:%lli].\n",
357 temp_inst->readPC(), temp_inst->seqNum);
358
359 moveToReady(inst_entry);
360
361 if (temp_inst == inst) {
362 found_inst = true;
363 }
364
365 instsToReplay.pop_front();
366 }
367
368 assert(found_inst);
369}
370
371template <class MemDepPred, class Impl>
372void
373MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
374{
375 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
376 "[sn:%lli].\n",
377 inst->readPC(), inst->seqNum);
378
379 unsigned tid = inst->threadNumber;
380
381 // Remove the instruction from the hash and the list.
382 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
383
384 assert(hash_it != memDepHash.end());
385
386 instList[tid].erase((*hash_it).second->listIt);
387
388 (*hash_it).second = NULL;
389
390 memDepHash.erase(hash_it);
391#ifdef DEBUG
392 MemDepEntry::memdep_erase++;
393#endif
394}
395
396template <class MemDepPred, class Impl>
397void
398MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
399{
400 wakeDependents(inst);
401 completed(inst);
402
403 InstSeqNum barr_sn = inst->seqNum;
404
405 if (inst->isMemBarrier()) {
406 assert(loadBarrier && storeBarrier);
407 if (loadBarrierSN == barr_sn)
408 loadBarrier = false;
409 if (storeBarrierSN == barr_sn)
410 storeBarrier = false;
411 } else if (inst->isWriteBarrier()) {
412 assert(storeBarrier);
413 if (storeBarrierSN == barr_sn)
414 storeBarrier = false;
415 }
416}
417
418template <class MemDepPred, class Impl>
419void
420MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
421{
422 // Only stores and barriers have dependents.
423 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
424 return;
425 }
426
427 MemDepEntryPtr inst_entry = findInHash(inst);
428
429 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
430 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
431
432 if (!woken_inst->inst) {
433 // Potentially removed mem dep entries could be on this list
434 continue;
435 }
436
437 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
438 "[sn:%lli].\n",
439 woken_inst->inst->seqNum);
440
441 if (woken_inst->regsReady && !woken_inst->squashed) {
442 moveToReady(woken_inst);
443 } else {
444 woken_inst->memDepReady = true;
445 }
446 }
447
448 inst_entry->dependInsts.clear();
449}
450
451template <class MemDepPred, class Impl>
452void
453MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
454 unsigned tid)
455{
456 if (!instsToReplay.empty()) {
457 ListIt replay_it = instsToReplay.begin();
458 while (replay_it != instsToReplay.end()) {
459 if ((*replay_it)->threadNumber == tid &&
460 (*replay_it)->seqNum > squashed_num) {
461 instsToReplay.erase(replay_it++);
462 } else {
463 ++replay_it;
464 }
465 }
466 }
467
468 ListIt squash_it = instList[tid].end();
469 --squash_it;
470
471 MemDepHashIt hash_it;
472
473 while (!instList[tid].empty() &&
474 (*squash_it)->seqNum > squashed_num) {
475
476 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
477 (*squash_it)->seqNum);
478
479 hash_it = memDepHash.find((*squash_it)->seqNum);
480
481 assert(hash_it != memDepHash.end());
482
483 (*hash_it).second->squashed = true;
484
485 (*hash_it).second = NULL;
486
487 memDepHash.erase(hash_it);
488#ifdef DEBUG
489 MemDepEntry::memdep_erase++;
490#endif
491
492 instList[tid].erase(squash_it--);
493 }
494
495 // Tell the dependency predictor to squash as well.
496 depPred.squash(squashed_num, tid);
497}
498
499template <class MemDepPred, class Impl>
500void
501MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
502 DynInstPtr &violating_load)
503{
504 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
505 " load: %#x, store: %#x\n", violating_load->readPC(),
506 store_inst->readPC());
507 // Tell the memory dependence unit of the violation.
508 depPred.violation(violating_load->readPC(), store_inst->readPC());
509}
510
511template <class MemDepPred, class Impl>
512void
513MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
514{
515 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
516 inst->readPC(), inst->seqNum);
517
518 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
519}
520
521template <class MemDepPred, class Impl>
522inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
523MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
524{
525 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
526
527 assert(hash_it != memDepHash.end());
528
529 return (*hash_it).second;
530}
531
532template <class MemDepPred, class Impl>
533inline void
534MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
535{
536 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
537 "to the ready list.\n", woken_inst_entry->inst->seqNum);
538
539 assert(!woken_inst_entry->squashed);
540
541 iqPtr->addReadyMemInst(woken_inst_entry->inst);
542}
543
544
545template <class MemDepPred, class Impl>
546void
547MemDepUnit<MemDepPred, Impl>::dumpLists()
548{
549 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
550 cprintf("Instruction list %i size: %i\n",
551 tid, instList[tid].size());
552
553 ListIt inst_list_it = instList[tid].begin();
554 int num = 0;
555
556 while (inst_list_it != instList[tid].end()) {
557 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
558 "Squashed:%i\n\n",
559 num, (*inst_list_it)->readPC(),
560 (*inst_list_it)->seqNum,
561 (*inst_list_it)->threadNumber,
562 (*inst_list_it)->isIssued(),
563 (*inst_list_it)->isSquashed());
564 inst_list_it++;
565 ++num;
566 }
567 }
568
569 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
570
571#ifdef DEBUG
572 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
573#endif
574}
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