mem_dep_unit_impl.hh (3125:febd811bccc6) | mem_dep_unit_impl.hh (3500:8d5e32b3bc2e) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#include <map> 32 33#include "cpu/o3/inst_queue.hh" 34#include "cpu/o3/mem_dep_unit.hh" 35 36template <class MemDepPred, class Impl> | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#include <map> 32 33#include "cpu/o3/inst_queue.hh" 34#include "cpu/o3/mem_dep_unit.hh" 35 36template <class MemDepPred, class Impl> |
37MemDepUnit<MemDepPred, Impl>::MemDepUnit() 38 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 39 storeBarrierSN(0), iqPtr(NULL) 40{ 41} 42 43template <class MemDepPred, class Impl> |
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37MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) 38 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 39 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 40{ 41 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 42} 43 44template <class MemDepPred, class Impl> --- 110 unchanged lines hidden (view full) --- 155 instList[tid].push_back(inst); 156 157 inst_entry->listIt = --(instList[tid].end()); 158 159 // Check any barriers and the dependence predictor for any 160 // producing memrefs/stores. 161 InstSeqNum producing_store; 162 if (inst->isLoad() && loadBarrier) { | 44MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) 45 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 46 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 47{ 48 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 49} 50 51template <class MemDepPred, class Impl> --- 110 unchanged lines hidden (view full) --- 162 instList[tid].push_back(inst); 163 164 inst_entry->listIt = --(instList[tid].end()); 165 166 // Check any barriers and the dependence predictor for any 167 // producing memrefs/stores. 168 InstSeqNum producing_store; 169 if (inst->isLoad() && loadBarrier) { |
170 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 171 loadBarrierSN); |
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163 producing_store = loadBarrierSN; 164 } else if (inst->isStore() && storeBarrier) { | 172 producing_store = loadBarrierSN; 173 } else if (inst->isStore() && storeBarrier) { |
174 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 175 storeBarrierSN); |
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165 producing_store = storeBarrierSN; 166 } else { 167 producing_store = depPred.checkInst(inst->readPC()); 168 } 169 170 MemDepEntryPtr store_entry = NULL; 171 172 // If there is a producing store, try to find the entry. 173 if (producing_store != 0) { | 176 producing_store = storeBarrierSN; 177 } else { 178 producing_store = depPred.checkInst(inst->readPC()); 179 } 180 181 MemDepEntryPtr store_entry = NULL; 182 183 // If there is a producing store, try to find the entry. 184 if (producing_store != 0) { |
185 DPRINTF(MemDepUnit, "Searching for producer\n"); |
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174 MemDepHashIt hash_it = memDepHash.find(producing_store); 175 176 if (hash_it != memDepHash.end()) { 177 store_entry = (*hash_it).second; | 186 MemDepHashIt hash_it = memDepHash.find(producing_store); 187 188 if (hash_it != memDepHash.end()) { 189 store_entry = (*hash_it).second; |
190 DPRINTF(MemDepUnit, "Proucer found\n"); |
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178 } 179 } 180 181 // If no store entry, then instruction can issue as soon as the registers 182 // are ready. 183 if (!store_entry) { 184 DPRINTF(MemDepUnit, "No dependency for inst PC " 185 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); --- 389 unchanged lines hidden --- | 191 } 192 } 193 194 // If no store entry, then instruction can issue as soon as the registers 195 // are ready. 196 if (!store_entry) { 197 DPRINTF(MemDepUnit, "No dependency for inst PC " 198 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); --- 389 unchanged lines hidden --- |