1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35#include "params/DerivO3CPU.hh"
36
37template <class MemDepPred, class Impl>
38MemDepUnit<MemDepPred, Impl>::MemDepUnit()
39 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
40 storeBarrierSN(0), iqPtr(NULL)
41{
42}
43
44template <class MemDepPred, class Impl>
45MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
46 : _name(params->name + ".memdepunit"),
47 depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
48 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
49{
50 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
51}
52
53template <class MemDepPred, class Impl>
54MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
55{
56 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
57
58 ListIt inst_list_it = instList[tid].begin();
59
60 MemDepHashIt hash_it;
61
62 while (!instList[tid].empty()) {
63 hash_it = memDepHash.find((*inst_list_it)->seqNum);
64
65 assert(hash_it != memDepHash.end());
66
67 memDepHash.erase(hash_it);
68
69 instList[tid].erase(inst_list_it++);
70 }
71 }
72
73#ifdef DEBUG
74 assert(MemDepEntry::memdep_count == 0);
75#endif
76}
77
78template <class MemDepPred, class Impl>
79void
80MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
81{
82 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
83
84 _name = csprintf("%s.memDep%d", params->name, tid);
85 id = tid;
86
87 depPred.init(params->SSITSize, params->LFSTSize);
88}
89
90template <class MemDepPred, class Impl>
91void
92MemDepUnit<MemDepPred, Impl>::regStats()
93{
94 insertedLoads
95 .name(name() + ".insertedLoads")
96 .desc("Number of loads inserted to the mem dependence unit.");
97
98 insertedStores
99 .name(name() + ".insertedStores")
100 .desc("Number of stores inserted to the mem dependence unit.");
101
102 conflictingLoads
103 .name(name() + ".conflictingLoads")
104 .desc("Number of conflicting loads.");
105
106 conflictingStores
107 .name(name() + ".conflictingStores")
108 .desc("Number of conflicting stores.");
109}
110
111template <class MemDepPred, class Impl>
112void
113MemDepUnit<MemDepPred, Impl>::switchOut()
114{
115 assert(instList[0].empty());
116 assert(instsToReplay.empty());
117 assert(memDepHash.empty());
118 // Clear any state.
119 for (int i = 0; i < Impl::MaxThreads; ++i) {
120 instList[i].clear();
121 }
122 instsToReplay.clear();
123 memDepHash.clear();
124}
125
126template <class MemDepPred, class Impl>
127void
128MemDepUnit<MemDepPred, Impl>::takeOverFrom()
129{
130 // Be sure to reset all state.
131 loadBarrier = storeBarrier = false;
132 loadBarrierSN = storeBarrierSN = 0;
133 depPred.clear();
134}
135
136template <class MemDepPred, class Impl>
137void
138MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
139{
140 iqPtr = iq_ptr;
141}
142
143template <class MemDepPred, class Impl>
144void
145MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
146{
147 ThreadID tid = inst->threadNumber;
148
149 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
150
151 // Add the MemDepEntry to the hash.
152 memDepHash.insert(
153 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
154#ifdef DEBUG
155 MemDepEntry::memdep_insert++;
156#endif
157
158 instList[tid].push_back(inst);
159
160 inst_entry->listIt = --(instList[tid].end());
161
162 // Check any barriers and the dependence predictor for any
163 // producing memrefs/stores.
164 InstSeqNum producing_store;
165 if (inst->isLoad() && loadBarrier) {
166 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
167 loadBarrierSN);
168 producing_store = loadBarrierSN;
169 } else if (inst->isStore() && storeBarrier) {
170 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
171 storeBarrierSN);
172 producing_store = storeBarrierSN;
173 } else {
174 producing_store = depPred.checkInst(inst->instAddr());
175 }
176
177 MemDepEntryPtr store_entry = NULL;
178
179 // If there is a producing store, try to find the entry.
180 if (producing_store != 0) {
181 DPRINTF(MemDepUnit, "Searching for producer\n");
182 MemDepHashIt hash_it = memDepHash.find(producing_store);
183
184 if (hash_it != memDepHash.end()) {
185 store_entry = (*hash_it).second;
186 DPRINTF(MemDepUnit, "Proucer found\n");
187 }
188 }
189
190 // If no store entry, then instruction can issue as soon as the registers
191 // are ready.
192 if (!store_entry) {
193 DPRINTF(MemDepUnit, "No dependency for inst PC "
194 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
195
196 inst_entry->memDepReady = true;
197
198 if (inst->readyToIssue()) {
199 inst_entry->regsReady = true;
200
201 moveToReady(inst_entry);
202 }
203 } else {
204 // Otherwise make the instruction dependent on the store/barrier.
205 DPRINTF(MemDepUnit, "Adding to dependency list; "
206 "inst PC %s is dependent on [sn:%lli].\n",
207 inst->pcState(), producing_store);
208
209 if (inst->readyToIssue()) {
210 inst_entry->regsReady = true;
211 }
212
213 // Clear the bit saying this instruction can issue.
214 inst->clearCanIssue();
215
216 // Add this instruction to the list of dependents.
217 store_entry->dependInsts.push_back(inst_entry);
218
219 if (inst->isLoad()) {
220 ++conflictingLoads;
221 } else {
222 ++conflictingStores;
223 }
224 }
225
226 if (inst->isStore()) {
227 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
228 inst->pcState(), inst->seqNum);
229
230 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
231
232 ++insertedStores;
233 } else if (inst->isLoad()) {
234 ++insertedLoads;
235 } else {
236 panic("Unknown type! (most likely a barrier).");
237 }
238}
239
240template <class MemDepPred, class Impl>
241void
242MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
243{
244 ThreadID tid = inst->threadNumber;
245
246 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
247
248 // Insert the MemDepEntry into the hash.
249 memDepHash.insert(
250 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
251#ifdef DEBUG
252 MemDepEntry::memdep_insert++;
253#endif
254
255 // Add the instruction to the list.
256 instList[tid].push_back(inst);
257
258 inst_entry->listIt = --(instList[tid].end());
259
260 // Might want to turn this part into an inline function or something.
261 // It's shared between both insert functions.
262 if (inst->isStore()) {
263 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
264 inst->pcState(), inst->seqNum);
265
266 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
267
268 ++insertedStores;
269 } else if (inst->isLoad()) {
270 ++insertedLoads;
271 } else {
272 panic("Unknown type! (most likely a barrier).");
273 }
274}
275
276template <class MemDepPred, class Impl>
277void
278MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
279{
280 InstSeqNum barr_sn = barr_inst->seqNum;
281 // Memory barriers block loads and stores, write barriers only stores.
282 if (barr_inst->isMemBarrier()) {
283 loadBarrier = true;
284 loadBarrierSN = barr_sn;
285 storeBarrier = true;
286 storeBarrierSN = barr_sn;
287 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
288 } else if (barr_inst->isWriteBarrier()) {
289 storeBarrier = true;
290 storeBarrierSN = barr_sn;
291 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
292 }
293
294 ThreadID tid = barr_inst->threadNumber;
295
296 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
297
298 // Add the MemDepEntry to the hash.
299 memDepHash.insert(
300 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
301#ifdef DEBUG
302 MemDepEntry::memdep_insert++;
303#endif
304
305 // Add the instruction to the instruction list.
306 instList[tid].push_back(barr_inst);
307
308 inst_entry->listIt = --(instList[tid].end());
309}
310
311template <class MemDepPred, class Impl>
312void
313MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
314{
315 DPRINTF(MemDepUnit, "Marking registers as ready for "
316 "instruction PC %s [sn:%lli].\n",
317 inst->pcState(), inst->seqNum);
318
319 MemDepEntryPtr inst_entry = findInHash(inst);
320
321 inst_entry->regsReady = true;
322
323 if (inst_entry->memDepReady) {
324 DPRINTF(MemDepUnit, "Instruction has its memory "
325 "dependencies resolved, adding it to the ready list.\n");
326
327 moveToReady(inst_entry);
328 } else {
329 DPRINTF(MemDepUnit, "Instruction still waiting on "
330 "memory dependency.\n");
331 }
332}
333
334template <class MemDepPred, class Impl>
335void
336MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
337{
338 DPRINTF(MemDepUnit, "Marking non speculative "
339 "instruction PC %s as ready [sn:%lli].\n",
340 inst->pcState(), inst->seqNum);
341
342 MemDepEntryPtr inst_entry = findInHash(inst);
343
344 moveToReady(inst_entry);
345}
346
347template <class MemDepPred, class Impl>
348void
349MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
350{
351 instsToReplay.push_back(inst);
352}
353
354template <class MemDepPred, class Impl>
355void
356MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
357{
358 DynInstPtr temp_inst;
359
360 // For now this replay function replays all waiting memory ops.
361 while (!instsToReplay.empty()) {
362 temp_inst = instsToReplay.front();
363
364 MemDepEntryPtr inst_entry = findInHash(temp_inst);
365
366 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
367 temp_inst->pcState(), temp_inst->seqNum);
368
369 moveToReady(inst_entry);
370
371 instsToReplay.pop_front();
372 }
373}
374
375template <class MemDepPred, class Impl>
376void
377MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
378{
379 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
380 inst->pcState(), inst->seqNum);
381
382 ThreadID tid = inst->threadNumber;
383
384 // Remove the instruction from the hash and the list.
385 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
386
387 assert(hash_it != memDepHash.end());
388
389 instList[tid].erase((*hash_it).second->listIt);
390
391 (*hash_it).second = NULL;
392
393 memDepHash.erase(hash_it);
394#ifdef DEBUG
395 MemDepEntry::memdep_erase++;
396#endif
397}
398
399template <class MemDepPred, class Impl>
400void
401MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
402{
403 wakeDependents(inst);
404 completed(inst);
405
406 InstSeqNum barr_sn = inst->seqNum;
407
408 if (inst->isMemBarrier()) {
409 assert(loadBarrier && storeBarrier);
410 if (loadBarrierSN == barr_sn)
411 loadBarrier = false;
412 if (storeBarrierSN == barr_sn)
413 storeBarrier = false;
414 } else if (inst->isWriteBarrier()) {
415 assert(storeBarrier);
416 if (storeBarrierSN == barr_sn)
417 storeBarrier = false;
418 }
419}
420
421template <class MemDepPred, class Impl>
422void
423MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
424{
425 // Only stores and barriers have dependents.
426 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
427 return;
428 }
429
430 MemDepEntryPtr inst_entry = findInHash(inst);
431
432 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
433 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
434
435 if (!woken_inst->inst) {
436 // Potentially removed mem dep entries could be on this list
437 continue;
438 }
439
440 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
441 "[sn:%lli].\n",
442 woken_inst->inst->seqNum);
443
444 if (woken_inst->regsReady && !woken_inst->squashed) {
445 moveToReady(woken_inst);
446 } else {
447 woken_inst->memDepReady = true;
448 }
449 }
450
451 inst_entry->dependInsts.clear();
452}
453
454template <class MemDepPred, class Impl>
455void
456MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
457 ThreadID tid)
458{
459 if (!instsToReplay.empty()) {
460 ListIt replay_it = instsToReplay.begin();
461 while (replay_it != instsToReplay.end()) {
462 if ((*replay_it)->threadNumber == tid &&
463 (*replay_it)->seqNum > squashed_num) {
464 instsToReplay.erase(replay_it++);
465 } else {
466 ++replay_it;
467 }
468 }
469 }
470
471 ListIt squash_it = instList[tid].end();
472 --squash_it;
473
474 MemDepHashIt hash_it;
475
476 while (!instList[tid].empty() &&
477 (*squash_it)->seqNum > squashed_num) {
478
479 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
480 (*squash_it)->seqNum);
481
482 hash_it = memDepHash.find((*squash_it)->seqNum);
483
484 assert(hash_it != memDepHash.end());
485
486 (*hash_it).second->squashed = true;
487
488 (*hash_it).second = NULL;
489
490 memDepHash.erase(hash_it);
491#ifdef DEBUG
492 MemDepEntry::memdep_erase++;
493#endif
494
495 instList[tid].erase(squash_it--);
496 }
497
498 // Tell the dependency predictor to squash as well.
499 depPred.squash(squashed_num, tid);
500}
501
502template <class MemDepPred, class Impl>
503void
504MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
505 DynInstPtr &violating_load)
506{
507 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
508 " load: %#x, store: %#x\n", violating_load->instAddr(),
509 store_inst->instAddr());
510 // Tell the memory dependence unit of the violation.
511 depPred.violation(violating_load->instAddr(), store_inst->instAddr());
512}
513
514template <class MemDepPred, class Impl>
515void
516MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
517{
518 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
519 inst->instAddr(), inst->seqNum);
520
521 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
522}
523
524template <class MemDepPred, class Impl>
525inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
526MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
527{
528 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
529
530 assert(hash_it != memDepHash.end());
531
532 return (*hash_it).second;
533}
534
535template <class MemDepPred, class Impl>
536inline void
537MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
538{
539 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
540 "to the ready list.\n", woken_inst_entry->inst->seqNum);
541
542 assert(!woken_inst_entry->squashed);
543
544 iqPtr->addReadyMemInst(woken_inst_entry->inst);
545}
546
547
548template <class MemDepPred, class Impl>
549void
550MemDepUnit<MemDepPred, Impl>::dumpLists()
551{
552 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
553 cprintf("Instruction list %i size: %i\n",
554 tid, instList[tid].size());
555
556 ListIt inst_list_it = instList[tid].begin();
557 int num = 0;
558
559 while (inst_list_it != instList[tid].end()) {
560 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
561 "Squashed:%i\n\n",
562 num, (*inst_list_it)->pcState(),
563 (*inst_list_it)->seqNum,
564 (*inst_list_it)->threadNumber,
565 (*inst_list_it)->isIssued(),
566 (*inst_list_it)->isSquashed());
567 inst_list_it++;
568 ++num;
569 }
570 }
571
572 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
573
574#ifdef DEBUG
575 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
576#endif
577}
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35#include "params/DerivO3CPU.hh"
36
37template <class MemDepPred, class Impl>
38MemDepUnit<MemDepPred, Impl>::MemDepUnit()
39 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
40 storeBarrierSN(0), iqPtr(NULL)
41{
42}
43
44template <class MemDepPred, class Impl>
45MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
46 : _name(params->name + ".memdepunit"),
47 depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
48 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
49{
50 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
51}
52
53template <class MemDepPred, class Impl>
54MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
55{
56 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
57
58 ListIt inst_list_it = instList[tid].begin();
59
60 MemDepHashIt hash_it;
61
62 while (!instList[tid].empty()) {
63 hash_it = memDepHash.find((*inst_list_it)->seqNum);
64
65 assert(hash_it != memDepHash.end());
66
67 memDepHash.erase(hash_it);
68
69 instList[tid].erase(inst_list_it++);
70 }
71 }
72
73#ifdef DEBUG
74 assert(MemDepEntry::memdep_count == 0);
75#endif
76}
77
78template <class MemDepPred, class Impl>
79void
80MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
81{
82 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
83
84 _name = csprintf("%s.memDep%d", params->name, tid);
85 id = tid;
86
87 depPred.init(params->SSITSize, params->LFSTSize);
88}
89
90template <class MemDepPred, class Impl>
91void
92MemDepUnit<MemDepPred, Impl>::regStats()
93{
94 insertedLoads
95 .name(name() + ".insertedLoads")
96 .desc("Number of loads inserted to the mem dependence unit.");
97
98 insertedStores
99 .name(name() + ".insertedStores")
100 .desc("Number of stores inserted to the mem dependence unit.");
101
102 conflictingLoads
103 .name(name() + ".conflictingLoads")
104 .desc("Number of conflicting loads.");
105
106 conflictingStores
107 .name(name() + ".conflictingStores")
108 .desc("Number of conflicting stores.");
109}
110
111template <class MemDepPred, class Impl>
112void
113MemDepUnit<MemDepPred, Impl>::switchOut()
114{
115 assert(instList[0].empty());
116 assert(instsToReplay.empty());
117 assert(memDepHash.empty());
118 // Clear any state.
119 for (int i = 0; i < Impl::MaxThreads; ++i) {
120 instList[i].clear();
121 }
122 instsToReplay.clear();
123 memDepHash.clear();
124}
125
126template <class MemDepPred, class Impl>
127void
128MemDepUnit<MemDepPred, Impl>::takeOverFrom()
129{
130 // Be sure to reset all state.
131 loadBarrier = storeBarrier = false;
132 loadBarrierSN = storeBarrierSN = 0;
133 depPred.clear();
134}
135
136template <class MemDepPred, class Impl>
137void
138MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
139{
140 iqPtr = iq_ptr;
141}
142
143template <class MemDepPred, class Impl>
144void
145MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
146{
147 ThreadID tid = inst->threadNumber;
148
149 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
150
151 // Add the MemDepEntry to the hash.
152 memDepHash.insert(
153 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
154#ifdef DEBUG
155 MemDepEntry::memdep_insert++;
156#endif
157
158 instList[tid].push_back(inst);
159
160 inst_entry->listIt = --(instList[tid].end());
161
162 // Check any barriers and the dependence predictor for any
163 // producing memrefs/stores.
164 InstSeqNum producing_store;
165 if (inst->isLoad() && loadBarrier) {
166 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
167 loadBarrierSN);
168 producing_store = loadBarrierSN;
169 } else if (inst->isStore() && storeBarrier) {
170 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
171 storeBarrierSN);
172 producing_store = storeBarrierSN;
173 } else {
174 producing_store = depPred.checkInst(inst->instAddr());
175 }
176
177 MemDepEntryPtr store_entry = NULL;
178
179 // If there is a producing store, try to find the entry.
180 if (producing_store != 0) {
181 DPRINTF(MemDepUnit, "Searching for producer\n");
182 MemDepHashIt hash_it = memDepHash.find(producing_store);
183
184 if (hash_it != memDepHash.end()) {
185 store_entry = (*hash_it).second;
186 DPRINTF(MemDepUnit, "Proucer found\n");
187 }
188 }
189
190 // If no store entry, then instruction can issue as soon as the registers
191 // are ready.
192 if (!store_entry) {
193 DPRINTF(MemDepUnit, "No dependency for inst PC "
194 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
195
196 inst_entry->memDepReady = true;
197
198 if (inst->readyToIssue()) {
199 inst_entry->regsReady = true;
200
201 moveToReady(inst_entry);
202 }
203 } else {
204 // Otherwise make the instruction dependent on the store/barrier.
205 DPRINTF(MemDepUnit, "Adding to dependency list; "
206 "inst PC %s is dependent on [sn:%lli].\n",
207 inst->pcState(), producing_store);
208
209 if (inst->readyToIssue()) {
210 inst_entry->regsReady = true;
211 }
212
213 // Clear the bit saying this instruction can issue.
214 inst->clearCanIssue();
215
216 // Add this instruction to the list of dependents.
217 store_entry->dependInsts.push_back(inst_entry);
218
219 if (inst->isLoad()) {
220 ++conflictingLoads;
221 } else {
222 ++conflictingStores;
223 }
224 }
225
226 if (inst->isStore()) {
227 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
228 inst->pcState(), inst->seqNum);
229
230 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
231
232 ++insertedStores;
233 } else if (inst->isLoad()) {
234 ++insertedLoads;
235 } else {
236 panic("Unknown type! (most likely a barrier).");
237 }
238}
239
240template <class MemDepPred, class Impl>
241void
242MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
243{
244 ThreadID tid = inst->threadNumber;
245
246 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
247
248 // Insert the MemDepEntry into the hash.
249 memDepHash.insert(
250 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
251#ifdef DEBUG
252 MemDepEntry::memdep_insert++;
253#endif
254
255 // Add the instruction to the list.
256 instList[tid].push_back(inst);
257
258 inst_entry->listIt = --(instList[tid].end());
259
260 // Might want to turn this part into an inline function or something.
261 // It's shared between both insert functions.
262 if (inst->isStore()) {
263 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
264 inst->pcState(), inst->seqNum);
265
266 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
267
268 ++insertedStores;
269 } else if (inst->isLoad()) {
270 ++insertedLoads;
271 } else {
272 panic("Unknown type! (most likely a barrier).");
273 }
274}
275
276template <class MemDepPred, class Impl>
277void
278MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
279{
280 InstSeqNum barr_sn = barr_inst->seqNum;
281 // Memory barriers block loads and stores, write barriers only stores.
282 if (barr_inst->isMemBarrier()) {
283 loadBarrier = true;
284 loadBarrierSN = barr_sn;
285 storeBarrier = true;
286 storeBarrierSN = barr_sn;
287 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
288 } else if (barr_inst->isWriteBarrier()) {
289 storeBarrier = true;
290 storeBarrierSN = barr_sn;
291 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
292 }
293
294 ThreadID tid = barr_inst->threadNumber;
295
296 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
297
298 // Add the MemDepEntry to the hash.
299 memDepHash.insert(
300 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
301#ifdef DEBUG
302 MemDepEntry::memdep_insert++;
303#endif
304
305 // Add the instruction to the instruction list.
306 instList[tid].push_back(barr_inst);
307
308 inst_entry->listIt = --(instList[tid].end());
309}
310
311template <class MemDepPred, class Impl>
312void
313MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
314{
315 DPRINTF(MemDepUnit, "Marking registers as ready for "
316 "instruction PC %s [sn:%lli].\n",
317 inst->pcState(), inst->seqNum);
318
319 MemDepEntryPtr inst_entry = findInHash(inst);
320
321 inst_entry->regsReady = true;
322
323 if (inst_entry->memDepReady) {
324 DPRINTF(MemDepUnit, "Instruction has its memory "
325 "dependencies resolved, adding it to the ready list.\n");
326
327 moveToReady(inst_entry);
328 } else {
329 DPRINTF(MemDepUnit, "Instruction still waiting on "
330 "memory dependency.\n");
331 }
332}
333
334template <class MemDepPred, class Impl>
335void
336MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
337{
338 DPRINTF(MemDepUnit, "Marking non speculative "
339 "instruction PC %s as ready [sn:%lli].\n",
340 inst->pcState(), inst->seqNum);
341
342 MemDepEntryPtr inst_entry = findInHash(inst);
343
344 moveToReady(inst_entry);
345}
346
347template <class MemDepPred, class Impl>
348void
349MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
350{
351 instsToReplay.push_back(inst);
352}
353
354template <class MemDepPred, class Impl>
355void
356MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
357{
358 DynInstPtr temp_inst;
359
360 // For now this replay function replays all waiting memory ops.
361 while (!instsToReplay.empty()) {
362 temp_inst = instsToReplay.front();
363
364 MemDepEntryPtr inst_entry = findInHash(temp_inst);
365
366 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
367 temp_inst->pcState(), temp_inst->seqNum);
368
369 moveToReady(inst_entry);
370
371 instsToReplay.pop_front();
372 }
373}
374
375template <class MemDepPred, class Impl>
376void
377MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
378{
379 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
380 inst->pcState(), inst->seqNum);
381
382 ThreadID tid = inst->threadNumber;
383
384 // Remove the instruction from the hash and the list.
385 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
386
387 assert(hash_it != memDepHash.end());
388
389 instList[tid].erase((*hash_it).second->listIt);
390
391 (*hash_it).second = NULL;
392
393 memDepHash.erase(hash_it);
394#ifdef DEBUG
395 MemDepEntry::memdep_erase++;
396#endif
397}
398
399template <class MemDepPred, class Impl>
400void
401MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
402{
403 wakeDependents(inst);
404 completed(inst);
405
406 InstSeqNum barr_sn = inst->seqNum;
407
408 if (inst->isMemBarrier()) {
409 assert(loadBarrier && storeBarrier);
410 if (loadBarrierSN == barr_sn)
411 loadBarrier = false;
412 if (storeBarrierSN == barr_sn)
413 storeBarrier = false;
414 } else if (inst->isWriteBarrier()) {
415 assert(storeBarrier);
416 if (storeBarrierSN == barr_sn)
417 storeBarrier = false;
418 }
419}
420
421template <class MemDepPred, class Impl>
422void
423MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
424{
425 // Only stores and barriers have dependents.
426 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
427 return;
428 }
429
430 MemDepEntryPtr inst_entry = findInHash(inst);
431
432 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
433 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
434
435 if (!woken_inst->inst) {
436 // Potentially removed mem dep entries could be on this list
437 continue;
438 }
439
440 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
441 "[sn:%lli].\n",
442 woken_inst->inst->seqNum);
443
444 if (woken_inst->regsReady && !woken_inst->squashed) {
445 moveToReady(woken_inst);
446 } else {
447 woken_inst->memDepReady = true;
448 }
449 }
450
451 inst_entry->dependInsts.clear();
452}
453
454template <class MemDepPred, class Impl>
455void
456MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
457 ThreadID tid)
458{
459 if (!instsToReplay.empty()) {
460 ListIt replay_it = instsToReplay.begin();
461 while (replay_it != instsToReplay.end()) {
462 if ((*replay_it)->threadNumber == tid &&
463 (*replay_it)->seqNum > squashed_num) {
464 instsToReplay.erase(replay_it++);
465 } else {
466 ++replay_it;
467 }
468 }
469 }
470
471 ListIt squash_it = instList[tid].end();
472 --squash_it;
473
474 MemDepHashIt hash_it;
475
476 while (!instList[tid].empty() &&
477 (*squash_it)->seqNum > squashed_num) {
478
479 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
480 (*squash_it)->seqNum);
481
482 hash_it = memDepHash.find((*squash_it)->seqNum);
483
484 assert(hash_it != memDepHash.end());
485
486 (*hash_it).second->squashed = true;
487
488 (*hash_it).second = NULL;
489
490 memDepHash.erase(hash_it);
491#ifdef DEBUG
492 MemDepEntry::memdep_erase++;
493#endif
494
495 instList[tid].erase(squash_it--);
496 }
497
498 // Tell the dependency predictor to squash as well.
499 depPred.squash(squashed_num, tid);
500}
501
502template <class MemDepPred, class Impl>
503void
504MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
505 DynInstPtr &violating_load)
506{
507 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
508 " load: %#x, store: %#x\n", violating_load->instAddr(),
509 store_inst->instAddr());
510 // Tell the memory dependence unit of the violation.
511 depPred.violation(violating_load->instAddr(), store_inst->instAddr());
512}
513
514template <class MemDepPred, class Impl>
515void
516MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
517{
518 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
519 inst->instAddr(), inst->seqNum);
520
521 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
522}
523
524template <class MemDepPred, class Impl>
525inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
526MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
527{
528 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
529
530 assert(hash_it != memDepHash.end());
531
532 return (*hash_it).second;
533}
534
535template <class MemDepPred, class Impl>
536inline void
537MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
538{
539 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
540 "to the ready list.\n", woken_inst_entry->inst->seqNum);
541
542 assert(!woken_inst_entry->squashed);
543
544 iqPtr->addReadyMemInst(woken_inst_entry->inst);
545}
546
547
548template <class MemDepPred, class Impl>
549void
550MemDepUnit<MemDepPred, Impl>::dumpLists()
551{
552 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
553 cprintf("Instruction list %i size: %i\n",
554 tid, instList[tid].size());
555
556 ListIt inst_list_it = instList[tid].begin();
557 int num = 0;
558
559 while (inst_list_it != instList[tid].end()) {
560 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
561 "Squashed:%i\n\n",
562 num, (*inst_list_it)->pcState(),
563 (*inst_list_it)->seqNum,
564 (*inst_list_it)->threadNumber,
565 (*inst_list_it)->isIssued(),
566 (*inst_list_it)->isSquashed());
567 inst_list_it++;
568 ++num;
569 }
570 }
571
572 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
573
574#ifdef DEBUG
575 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
576#endif
577}