1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35
36template <class MemDepPred, class Impl>
37MemDepUnit<MemDepPred, Impl>::MemDepUnit()
38 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
39 storeBarrierSN(0), iqPtr(NULL)
40{
41}
42
43template <class MemDepPred, class Impl>
44MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
45 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
46 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
47{
48 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
49}
50
51template <class MemDepPred, class Impl>
52MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
53{
54 for (int tid=0; tid < Impl::MaxThreads; tid++) {
55
56 ListIt inst_list_it = instList[tid].begin();
57
58 MemDepHashIt hash_it;
59
60 while (!instList[tid].empty()) {
61 hash_it = memDepHash.find((*inst_list_it)->seqNum);
62
63 assert(hash_it != memDepHash.end());
64
65 memDepHash.erase(hash_it);
66
67 instList[tid].erase(inst_list_it++);
68 }
69 }
70
71#ifdef DEBUG
72 assert(MemDepEntry::memdep_count == 0);
73#endif
74}
75
76template <class MemDepPred, class Impl>
77std::string
78MemDepUnit<MemDepPred, Impl>::name() const
79{
80 return "memdepunit";
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
86{
87 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
88
89 id = tid;
90
91 depPred.init(params->SSITSize, params->LFSTSize);
92}
93
94template <class MemDepPred, class Impl>
95void
96MemDepUnit<MemDepPred, Impl>::regStats()
97{
98 insertedLoads
99 .name(name() + ".memDep.insertedLoads")
100 .desc("Number of loads inserted to the mem dependence unit.");
101
102 insertedStores
103 .name(name() + ".memDep.insertedStores")
104 .desc("Number of stores inserted to the mem dependence unit.");
105
106 conflictingLoads
107 .name(name() + ".memDep.conflictingLoads")
108 .desc("Number of conflicting loads.");
109
110 conflictingStores
111 .name(name() + ".memDep.conflictingStores")
112 .desc("Number of conflicting stores.");
113}
114
115template <class MemDepPred, class Impl>
116void
117MemDepUnit<MemDepPred, Impl>::switchOut()
118{
119 assert(instList[0].empty());
120 assert(instsToReplay.empty());
121 assert(memDepHash.empty());
122 // Clear any state.
123 for (int i = 0; i < Impl::MaxThreads; ++i) {
124 instList[i].clear();
125 }
126 instsToReplay.clear();
127 memDepHash.clear();
128}
129
130template <class MemDepPred, class Impl>
131void
132MemDepUnit<MemDepPred, Impl>::takeOverFrom()
133{
134 // Be sure to reset all state.
135 loadBarrier = storeBarrier = false;
136 loadBarrierSN = storeBarrierSN = 0;
137 depPred.clear();
138}
139
140template <class MemDepPred, class Impl>
141void
142MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
143{
144 iqPtr = iq_ptr;
145}
146
147template <class MemDepPred, class Impl>
148void
149MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
150{
151 unsigned tid = inst->threadNumber;
152
153 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
154
155 // Add the MemDepEntry to the hash.
156 memDepHash.insert(
157 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
158#ifdef DEBUG
159 MemDepEntry::memdep_insert++;
160#endif
161
162 instList[tid].push_back(inst);
163
164 inst_entry->listIt = --(instList[tid].end());
165
166 // Check any barriers and the dependence predictor for any
167 // producing memrefs/stores.
168 InstSeqNum producing_store;
169 if (inst->isLoad() && loadBarrier) {
170 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
171 loadBarrierSN);
172 producing_store = loadBarrierSN;
173 } else if (inst->isStore() && storeBarrier) {
174 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
175 storeBarrierSN);
176 producing_store = storeBarrierSN;
177 } else {
178 producing_store = depPred.checkInst(inst->readPC());
179 }
180
181 MemDepEntryPtr store_entry = NULL;
182
183 // If there is a producing store, try to find the entry.
184 if (producing_store != 0) {
185 DPRINTF(MemDepUnit, "Searching for producer\n");
186 MemDepHashIt hash_it = memDepHash.find(producing_store);
187
188 if (hash_it != memDepHash.end()) {
189 store_entry = (*hash_it).second;
190 DPRINTF(MemDepUnit, "Proucer found\n");
191 }
192 }
193
194 // If no store entry, then instruction can issue as soon as the registers
195 // are ready.
196 if (!store_entry) {
197 DPRINTF(MemDepUnit, "No dependency for inst PC "
198 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
199
200 inst_entry->memDepReady = true;
201
202 if (inst->readyToIssue()) {
203 inst_entry->regsReady = true;
204
205 moveToReady(inst_entry);
206 }
207 } else {
208 // Otherwise make the instruction dependent on the store/barrier.
209 DPRINTF(MemDepUnit, "Adding to dependency list; "
210 "inst PC %#x is dependent on [sn:%lli].\n",
211 inst->readPC(), producing_store);
212
213 if (inst->readyToIssue()) {
214 inst_entry->regsReady = true;
215 }
216
217 // Add this instruction to the list of dependents.
218 store_entry->dependInsts.push_back(inst_entry);
219
220 if (inst->isLoad()) {
221 ++conflictingLoads;
222 } else {
223 ++conflictingStores;
224 }
225 }
226
227 if (inst->isStore()) {
228 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
229 inst->readPC(), inst->seqNum);
230
231 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
232
233 ++insertedStores;
234 } else if (inst->isLoad()) {
235 ++insertedLoads;
236 } else {
237 panic("Unknown type! (most likely a barrier).");
238 }
239}
240
241template <class MemDepPred, class Impl>
242void
243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
244{
245 unsigned tid = inst->threadNumber;
246
247 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
248
249 // Insert the MemDepEntry into the hash.
250 memDepHash.insert(
251 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
252#ifdef DEBUG
253 MemDepEntry::memdep_insert++;
254#endif
255
256 // Add the instruction to the list.
257 instList[tid].push_back(inst);
258
259 inst_entry->listIt = --(instList[tid].end());
260
261 // Might want to turn this part into an inline function or something.
262 // It's shared between both insert functions.
263 if (inst->isStore()) {
264 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
265 inst->readPC(), inst->seqNum);
266
267 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
268
269 ++insertedStores;
270 } else if (inst->isLoad()) {
271 ++insertedLoads;
272 } else {
273 panic("Unknown type! (most likely a barrier).");
274 }
275}
276
277template <class MemDepPred, class Impl>
278void
279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
280{
281 InstSeqNum barr_sn = barr_inst->seqNum;
282 // Memory barriers block loads and stores, write barriers only stores.
283 if (barr_inst->isMemBarrier()) {
284 loadBarrier = true;
285 loadBarrierSN = barr_sn;
286 storeBarrier = true;
287 storeBarrierSN = barr_sn;
288 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
289 } else if (barr_inst->isWriteBarrier()) {
290 storeBarrier = true;
291 storeBarrierSN = barr_sn;
292 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
293 }
294
295 unsigned tid = barr_inst->threadNumber;
296
297 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
298
299 // Add the MemDepEntry to the hash.
300 memDepHash.insert(
301 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
302#ifdef DEBUG
303 MemDepEntry::memdep_insert++;
304#endif
305
306 // Add the instruction to the instruction list.
307 instList[tid].push_back(barr_inst);
308
309 inst_entry->listIt = --(instList[tid].end());
310}
311
312template <class MemDepPred, class Impl>
313void
314MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
315{
316 DPRINTF(MemDepUnit, "Marking registers as ready for "
317 "instruction PC %#x [sn:%lli].\n",
318 inst->readPC(), inst->seqNum);
319
320 MemDepEntryPtr inst_entry = findInHash(inst);
321
322 inst_entry->regsReady = true;
323
324 if (inst_entry->memDepReady) {
325 DPRINTF(MemDepUnit, "Instruction has its memory "
326 "dependencies resolved, adding it to the ready list.\n");
327
328 moveToReady(inst_entry);
329 } else {
330 DPRINTF(MemDepUnit, "Instruction still waiting on "
331 "memory dependency.\n");
332 }
333}
334
335template <class MemDepPred, class Impl>
336void
337MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
338{
339 DPRINTF(MemDepUnit, "Marking non speculative "
340 "instruction PC %#x as ready [sn:%lli].\n",
341 inst->readPC(), inst->seqNum);
342
343 MemDepEntryPtr inst_entry = findInHash(inst);
344
345 moveToReady(inst_entry);
346}
347
348template <class MemDepPred, class Impl>
349void
350MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
351{
352 instsToReplay.push_back(inst);
353}
354
355template <class MemDepPred, class Impl>
356void
357MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
358{
359 DynInstPtr temp_inst;
360 bool found_inst = false;
361
362 // For now this replay function replays all waiting memory ops.
363 while (!instsToReplay.empty()) {
364 temp_inst = instsToReplay.front();
365
366 MemDepEntryPtr inst_entry = findInHash(temp_inst);
367
368 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
369 "[sn:%lli].\n",
370 temp_inst->readPC(), temp_inst->seqNum);
371
372 moveToReady(inst_entry);
373
374 if (temp_inst == inst) {
375 found_inst = true;
376 }
377
378 instsToReplay.pop_front();
379 }
380
381 assert(found_inst);
382}
383
384template <class MemDepPred, class Impl>
385void
386MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
387{
388 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
389 "[sn:%lli].\n",
390 inst->readPC(), inst->seqNum);
391
392 unsigned tid = inst->threadNumber;
393
394 // Remove the instruction from the hash and the list.
395 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
396
397 assert(hash_it != memDepHash.end());
398
399 instList[tid].erase((*hash_it).second->listIt);
400
401 (*hash_it).second = NULL;
402
403 memDepHash.erase(hash_it);
404#ifdef DEBUG
405 MemDepEntry::memdep_erase++;
406#endif
407}
408
409template <class MemDepPred, class Impl>
410void
411MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
412{
413 wakeDependents(inst);
414 completed(inst);
415
416 InstSeqNum barr_sn = inst->seqNum;
417
418 if (inst->isMemBarrier()) {
419 assert(loadBarrier && storeBarrier);
420 if (loadBarrierSN == barr_sn)
421 loadBarrier = false;
422 if (storeBarrierSN == barr_sn)
423 storeBarrier = false;
424 } else if (inst->isWriteBarrier()) {
425 assert(storeBarrier);
426 if (storeBarrierSN == barr_sn)
427 storeBarrier = false;
428 }
429}
430
431template <class MemDepPred, class Impl>
432void
433MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
434{
435 // Only stores and barriers have dependents.
436 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
437 return;
438 }
439
440 MemDepEntryPtr inst_entry = findInHash(inst);
441
442 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
443 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
444
445 if (!woken_inst->inst) {
446 // Potentially removed mem dep entries could be on this list
447 continue;
448 }
449
450 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
451 "[sn:%lli].\n",
452 woken_inst->inst->seqNum);
453
454 if (woken_inst->regsReady && !woken_inst->squashed) {
455 moveToReady(woken_inst);
456 } else {
457 woken_inst->memDepReady = true;
458 }
459 }
460
461 inst_entry->dependInsts.clear();
462}
463
464template <class MemDepPred, class Impl>
465void
466MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
467 unsigned tid)
468{
469 if (!instsToReplay.empty()) {
470 ListIt replay_it = instsToReplay.begin();
471 while (replay_it != instsToReplay.end()) {
472 if ((*replay_it)->threadNumber == tid &&
473 (*replay_it)->seqNum > squashed_num) {
474 instsToReplay.erase(replay_it++);
475 } else {
476 ++replay_it;
477 }
478 }
479 }
480
481 ListIt squash_it = instList[tid].end();
482 --squash_it;
483
484 MemDepHashIt hash_it;
485
486 while (!instList[tid].empty() &&
487 (*squash_it)->seqNum > squashed_num) {
488
489 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
490 (*squash_it)->seqNum);
491
492 hash_it = memDepHash.find((*squash_it)->seqNum);
493
494 assert(hash_it != memDepHash.end());
495
496 (*hash_it).second->squashed = true;
497
498 (*hash_it).second = NULL;
499
500 memDepHash.erase(hash_it);
501#ifdef DEBUG
502 MemDepEntry::memdep_erase++;
503#endif
504
505 instList[tid].erase(squash_it--);
506 }
507
508 // Tell the dependency predictor to squash as well.
509 depPred.squash(squashed_num, tid);
510}
511
512template <class MemDepPred, class Impl>
513void
514MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
515 DynInstPtr &violating_load)
516{
517 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
518 " load: %#x, store: %#x\n", violating_load->readPC(),
519 store_inst->readPC());
520 // Tell the memory dependence unit of the violation.
521 depPred.violation(violating_load->readPC(), store_inst->readPC());
522}
523
524template <class MemDepPred, class Impl>
525void
526MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
527{
528 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
529 inst->readPC(), inst->seqNum);
530
531 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
532}
533
534template <class MemDepPred, class Impl>
535inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
536MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
537{
538 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
539
540 assert(hash_it != memDepHash.end());
541
542 return (*hash_it).second;
543}
544
545template <class MemDepPred, class Impl>
546inline void
547MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
548{
549 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
550 "to the ready list.\n", woken_inst_entry->inst->seqNum);
551
552 assert(!woken_inst_entry->squashed);
553
554 iqPtr->addReadyMemInst(woken_inst_entry->inst);
555}
556
557
558template <class MemDepPred, class Impl>
559void
560MemDepUnit<MemDepPred, Impl>::dumpLists()
561{
562 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
563 cprintf("Instruction list %i size: %i\n",
564 tid, instList[tid].size());
565
566 ListIt inst_list_it = instList[tid].begin();
567 int num = 0;
568
569 while (inst_list_it != instList[tid].end()) {
570 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
571 "Squashed:%i\n\n",
572 num, (*inst_list_it)->readPC(),
573 (*inst_list_it)->seqNum,
574 (*inst_list_it)->threadNumber,
575 (*inst_list_it)->isIssued(),
576 (*inst_list_it)->isSquashed());
577 inst_list_it++;
578 ++num;
579 }
580 }
581
582 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
583
584#ifdef DEBUG
585 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
586#endif
587}
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35
36template <class MemDepPred, class Impl>
37MemDepUnit<MemDepPred, Impl>::MemDepUnit()
38 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
39 storeBarrierSN(0), iqPtr(NULL)
40{
41}
42
43template <class MemDepPred, class Impl>
44MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
45 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
46 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
47{
48 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
49}
50
51template <class MemDepPred, class Impl>
52MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
53{
54 for (int tid=0; tid < Impl::MaxThreads; tid++) {
55
56 ListIt inst_list_it = instList[tid].begin();
57
58 MemDepHashIt hash_it;
59
60 while (!instList[tid].empty()) {
61 hash_it = memDepHash.find((*inst_list_it)->seqNum);
62
63 assert(hash_it != memDepHash.end());
64
65 memDepHash.erase(hash_it);
66
67 instList[tid].erase(inst_list_it++);
68 }
69 }
70
71#ifdef DEBUG
72 assert(MemDepEntry::memdep_count == 0);
73#endif
74}
75
76template <class MemDepPred, class Impl>
77std::string
78MemDepUnit<MemDepPred, Impl>::name() const
79{
80 return "memdepunit";
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
86{
87 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
88
89 id = tid;
90
91 depPred.init(params->SSITSize, params->LFSTSize);
92}
93
94template <class MemDepPred, class Impl>
95void
96MemDepUnit<MemDepPred, Impl>::regStats()
97{
98 insertedLoads
99 .name(name() + ".memDep.insertedLoads")
100 .desc("Number of loads inserted to the mem dependence unit.");
101
102 insertedStores
103 .name(name() + ".memDep.insertedStores")
104 .desc("Number of stores inserted to the mem dependence unit.");
105
106 conflictingLoads
107 .name(name() + ".memDep.conflictingLoads")
108 .desc("Number of conflicting loads.");
109
110 conflictingStores
111 .name(name() + ".memDep.conflictingStores")
112 .desc("Number of conflicting stores.");
113}
114
115template <class MemDepPred, class Impl>
116void
117MemDepUnit<MemDepPred, Impl>::switchOut()
118{
119 assert(instList[0].empty());
120 assert(instsToReplay.empty());
121 assert(memDepHash.empty());
122 // Clear any state.
123 for (int i = 0; i < Impl::MaxThreads; ++i) {
124 instList[i].clear();
125 }
126 instsToReplay.clear();
127 memDepHash.clear();
128}
129
130template <class MemDepPred, class Impl>
131void
132MemDepUnit<MemDepPred, Impl>::takeOverFrom()
133{
134 // Be sure to reset all state.
135 loadBarrier = storeBarrier = false;
136 loadBarrierSN = storeBarrierSN = 0;
137 depPred.clear();
138}
139
140template <class MemDepPred, class Impl>
141void
142MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
143{
144 iqPtr = iq_ptr;
145}
146
147template <class MemDepPred, class Impl>
148void
149MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
150{
151 unsigned tid = inst->threadNumber;
152
153 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
154
155 // Add the MemDepEntry to the hash.
156 memDepHash.insert(
157 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
158#ifdef DEBUG
159 MemDepEntry::memdep_insert++;
160#endif
161
162 instList[tid].push_back(inst);
163
164 inst_entry->listIt = --(instList[tid].end());
165
166 // Check any barriers and the dependence predictor for any
167 // producing memrefs/stores.
168 InstSeqNum producing_store;
169 if (inst->isLoad() && loadBarrier) {
170 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
171 loadBarrierSN);
172 producing_store = loadBarrierSN;
173 } else if (inst->isStore() && storeBarrier) {
174 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
175 storeBarrierSN);
176 producing_store = storeBarrierSN;
177 } else {
178 producing_store = depPred.checkInst(inst->readPC());
179 }
180
181 MemDepEntryPtr store_entry = NULL;
182
183 // If there is a producing store, try to find the entry.
184 if (producing_store != 0) {
185 DPRINTF(MemDepUnit, "Searching for producer\n");
186 MemDepHashIt hash_it = memDepHash.find(producing_store);
187
188 if (hash_it != memDepHash.end()) {
189 store_entry = (*hash_it).second;
190 DPRINTF(MemDepUnit, "Proucer found\n");
191 }
192 }
193
194 // If no store entry, then instruction can issue as soon as the registers
195 // are ready.
196 if (!store_entry) {
197 DPRINTF(MemDepUnit, "No dependency for inst PC "
198 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
199
200 inst_entry->memDepReady = true;
201
202 if (inst->readyToIssue()) {
203 inst_entry->regsReady = true;
204
205 moveToReady(inst_entry);
206 }
207 } else {
208 // Otherwise make the instruction dependent on the store/barrier.
209 DPRINTF(MemDepUnit, "Adding to dependency list; "
210 "inst PC %#x is dependent on [sn:%lli].\n",
211 inst->readPC(), producing_store);
212
213 if (inst->readyToIssue()) {
214 inst_entry->regsReady = true;
215 }
216
217 // Add this instruction to the list of dependents.
218 store_entry->dependInsts.push_back(inst_entry);
219
220 if (inst->isLoad()) {
221 ++conflictingLoads;
222 } else {
223 ++conflictingStores;
224 }
225 }
226
227 if (inst->isStore()) {
228 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
229 inst->readPC(), inst->seqNum);
230
231 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
232
233 ++insertedStores;
234 } else if (inst->isLoad()) {
235 ++insertedLoads;
236 } else {
237 panic("Unknown type! (most likely a barrier).");
238 }
239}
240
241template <class MemDepPred, class Impl>
242void
243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
244{
245 unsigned tid = inst->threadNumber;
246
247 MemDepEntryPtr inst_entry = new MemDepEntry(inst);
248
249 // Insert the MemDepEntry into the hash.
250 memDepHash.insert(
251 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
252#ifdef DEBUG
253 MemDepEntry::memdep_insert++;
254#endif
255
256 // Add the instruction to the list.
257 instList[tid].push_back(inst);
258
259 inst_entry->listIt = --(instList[tid].end());
260
261 // Might want to turn this part into an inline function or something.
262 // It's shared between both insert functions.
263 if (inst->isStore()) {
264 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
265 inst->readPC(), inst->seqNum);
266
267 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
268
269 ++insertedStores;
270 } else if (inst->isLoad()) {
271 ++insertedLoads;
272 } else {
273 panic("Unknown type! (most likely a barrier).");
274 }
275}
276
277template <class MemDepPred, class Impl>
278void
279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
280{
281 InstSeqNum barr_sn = barr_inst->seqNum;
282 // Memory barriers block loads and stores, write barriers only stores.
283 if (barr_inst->isMemBarrier()) {
284 loadBarrier = true;
285 loadBarrierSN = barr_sn;
286 storeBarrier = true;
287 storeBarrierSN = barr_sn;
288 DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
289 } else if (barr_inst->isWriteBarrier()) {
290 storeBarrier = true;
291 storeBarrierSN = barr_sn;
292 DPRINTF(MemDepUnit, "Inserted a write barrier\n");
293 }
294
295 unsigned tid = barr_inst->threadNumber;
296
297 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
298
299 // Add the MemDepEntry to the hash.
300 memDepHash.insert(
301 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
302#ifdef DEBUG
303 MemDepEntry::memdep_insert++;
304#endif
305
306 // Add the instruction to the instruction list.
307 instList[tid].push_back(barr_inst);
308
309 inst_entry->listIt = --(instList[tid].end());
310}
311
312template <class MemDepPred, class Impl>
313void
314MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
315{
316 DPRINTF(MemDepUnit, "Marking registers as ready for "
317 "instruction PC %#x [sn:%lli].\n",
318 inst->readPC(), inst->seqNum);
319
320 MemDepEntryPtr inst_entry = findInHash(inst);
321
322 inst_entry->regsReady = true;
323
324 if (inst_entry->memDepReady) {
325 DPRINTF(MemDepUnit, "Instruction has its memory "
326 "dependencies resolved, adding it to the ready list.\n");
327
328 moveToReady(inst_entry);
329 } else {
330 DPRINTF(MemDepUnit, "Instruction still waiting on "
331 "memory dependency.\n");
332 }
333}
334
335template <class MemDepPred, class Impl>
336void
337MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
338{
339 DPRINTF(MemDepUnit, "Marking non speculative "
340 "instruction PC %#x as ready [sn:%lli].\n",
341 inst->readPC(), inst->seqNum);
342
343 MemDepEntryPtr inst_entry = findInHash(inst);
344
345 moveToReady(inst_entry);
346}
347
348template <class MemDepPred, class Impl>
349void
350MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
351{
352 instsToReplay.push_back(inst);
353}
354
355template <class MemDepPred, class Impl>
356void
357MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
358{
359 DynInstPtr temp_inst;
360 bool found_inst = false;
361
362 // For now this replay function replays all waiting memory ops.
363 while (!instsToReplay.empty()) {
364 temp_inst = instsToReplay.front();
365
366 MemDepEntryPtr inst_entry = findInHash(temp_inst);
367
368 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
369 "[sn:%lli].\n",
370 temp_inst->readPC(), temp_inst->seqNum);
371
372 moveToReady(inst_entry);
373
374 if (temp_inst == inst) {
375 found_inst = true;
376 }
377
378 instsToReplay.pop_front();
379 }
380
381 assert(found_inst);
382}
383
384template <class MemDepPred, class Impl>
385void
386MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
387{
388 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
389 "[sn:%lli].\n",
390 inst->readPC(), inst->seqNum);
391
392 unsigned tid = inst->threadNumber;
393
394 // Remove the instruction from the hash and the list.
395 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
396
397 assert(hash_it != memDepHash.end());
398
399 instList[tid].erase((*hash_it).second->listIt);
400
401 (*hash_it).second = NULL;
402
403 memDepHash.erase(hash_it);
404#ifdef DEBUG
405 MemDepEntry::memdep_erase++;
406#endif
407}
408
409template <class MemDepPred, class Impl>
410void
411MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
412{
413 wakeDependents(inst);
414 completed(inst);
415
416 InstSeqNum barr_sn = inst->seqNum;
417
418 if (inst->isMemBarrier()) {
419 assert(loadBarrier && storeBarrier);
420 if (loadBarrierSN == barr_sn)
421 loadBarrier = false;
422 if (storeBarrierSN == barr_sn)
423 storeBarrier = false;
424 } else if (inst->isWriteBarrier()) {
425 assert(storeBarrier);
426 if (storeBarrierSN == barr_sn)
427 storeBarrier = false;
428 }
429}
430
431template <class MemDepPred, class Impl>
432void
433MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
434{
435 // Only stores and barriers have dependents.
436 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
437 return;
438 }
439
440 MemDepEntryPtr inst_entry = findInHash(inst);
441
442 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
443 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
444
445 if (!woken_inst->inst) {
446 // Potentially removed mem dep entries could be on this list
447 continue;
448 }
449
450 DPRINTF(MemDepUnit, "Waking up a dependent inst, "
451 "[sn:%lli].\n",
452 woken_inst->inst->seqNum);
453
454 if (woken_inst->regsReady && !woken_inst->squashed) {
455 moveToReady(woken_inst);
456 } else {
457 woken_inst->memDepReady = true;
458 }
459 }
460
461 inst_entry->dependInsts.clear();
462}
463
464template <class MemDepPred, class Impl>
465void
466MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
467 unsigned tid)
468{
469 if (!instsToReplay.empty()) {
470 ListIt replay_it = instsToReplay.begin();
471 while (replay_it != instsToReplay.end()) {
472 if ((*replay_it)->threadNumber == tid &&
473 (*replay_it)->seqNum > squashed_num) {
474 instsToReplay.erase(replay_it++);
475 } else {
476 ++replay_it;
477 }
478 }
479 }
480
481 ListIt squash_it = instList[tid].end();
482 --squash_it;
483
484 MemDepHashIt hash_it;
485
486 while (!instList[tid].empty() &&
487 (*squash_it)->seqNum > squashed_num) {
488
489 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
490 (*squash_it)->seqNum);
491
492 hash_it = memDepHash.find((*squash_it)->seqNum);
493
494 assert(hash_it != memDepHash.end());
495
496 (*hash_it).second->squashed = true;
497
498 (*hash_it).second = NULL;
499
500 memDepHash.erase(hash_it);
501#ifdef DEBUG
502 MemDepEntry::memdep_erase++;
503#endif
504
505 instList[tid].erase(squash_it--);
506 }
507
508 // Tell the dependency predictor to squash as well.
509 depPred.squash(squashed_num, tid);
510}
511
512template <class MemDepPred, class Impl>
513void
514MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
515 DynInstPtr &violating_load)
516{
517 DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
518 " load: %#x, store: %#x\n", violating_load->readPC(),
519 store_inst->readPC());
520 // Tell the memory dependence unit of the violation.
521 depPred.violation(violating_load->readPC(), store_inst->readPC());
522}
523
524template <class MemDepPred, class Impl>
525void
526MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
527{
528 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
529 inst->readPC(), inst->seqNum);
530
531 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
532}
533
534template <class MemDepPred, class Impl>
535inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
536MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
537{
538 MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
539
540 assert(hash_it != memDepHash.end());
541
542 return (*hash_it).second;
543}
544
545template <class MemDepPred, class Impl>
546inline void
547MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
548{
549 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
550 "to the ready list.\n", woken_inst_entry->inst->seqNum);
551
552 assert(!woken_inst_entry->squashed);
553
554 iqPtr->addReadyMemInst(woken_inst_entry->inst);
555}
556
557
558template <class MemDepPred, class Impl>
559void
560MemDepUnit<MemDepPred, Impl>::dumpLists()
561{
562 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
563 cprintf("Instruction list %i size: %i\n",
564 tid, instList[tid].size());
565
566 ListIt inst_list_it = instList[tid].begin();
567 int num = 0;
568
569 while (inst_list_it != instList[tid].end()) {
570 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
571 "Squashed:%i\n\n",
572 num, (*inst_list_it)->readPC(),
573 (*inst_list_it)->seqNum,
574 (*inst_list_it)->threadNumber,
575 (*inst_list_it)->isIssued(),
576 (*inst_list_it)->isSquashed());
577 inst_list_it++;
578 ++num;
579 }
580 }
581
582 cprintf("Memory dependence hash size: %i\n", memDepHash.size());
583
584#ifdef DEBUG
585 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
586#endif
587}