lsq_unit_impl.hh (9936:f00546aff354) lsq_unit_impl.hh (9944:4ff1c5c6dcbc)
1
2/*
3 * Copyright (c) 2010-2012 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
1
2/*
3 * Copyright (c) 2010-2012 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 28 unchanged lines hidden (view full) ---

37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44
45#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__
46#define __CPU_O3_LSQ_UNIT_IMPL_HH__
47
45#include "arch/generic/debugfaults.hh"
46#include "arch/locked_mem.hh"
47#include "base/str.hh"
48#include "config/the_isa.hh"
49#include "cpu/checker/cpu.hh"
50#include "cpu/o3/lsq.hh"
51#include "cpu/o3/lsq_unit.hh"
52#include "debug/Activity.hh"

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1284 const DynInstPtr &inst(storeQueue[store_idx].inst);
1285 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1286
1287 incrStIdx(store_idx);
1288 }
1289
1290 cprintf("\n");
1291}
48#include "arch/generic/debugfaults.hh"
49#include "arch/locked_mem.hh"
50#include "base/str.hh"
51#include "config/the_isa.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/lsq.hh"
54#include "cpu/o3/lsq_unit.hh"
55#include "debug/Activity.hh"

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1287 const DynInstPtr &inst(storeQueue[store_idx].inst);
1288 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum);
1289
1290 incrStIdx(store_idx);
1291 }
1292
1293 cprintf("\n");
1294}
1295
1296#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__