lsq_unit_impl.hh (9440:fdc91cab5760) | lsq_unit_impl.hh (9444:ab47fe7f03f0) |
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1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 52 unchanged lines hidden (view full) --- 61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 62{ 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ | 1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 52 unchanged lines hidden (view full) --- 61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 62{ 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ |
69 if (!lsqPtr->isSwitchedOut()) { 70 lsqPtr->writeback(inst, pkt); 71 } | 69 assert(!lsqPtr->cpu->switchedOut()); |
72 | 70 |
71 lsqPtr->writeback(inst, pkt); 72 |
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73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> --- 16 unchanged lines hidden (view full) --- 97 98 // If this is a split access, wait until all packets are received. 99 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 100 delete pkt->req; 101 delete pkt; 102 return; 103 } 104 | 73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> --- 16 unchanged lines hidden (view full) --- 97 98 // If this is a split access, wait until all packets are received. 99 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 100 delete pkt->req; 101 delete pkt; 102 return; 103 } 104 |
105 if (isSwitchedOut() || inst->isSquashed()) { | 105 assert(!cpu->switchedOut()); 106 if (inst->isSquashed()) { |
106 iewStage->decrWb(inst->seqNum); 107 } else { 108 if (!state->noWB) { 109 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 110 !state->isLoad) { 111 writeback(inst, pkt); 112 } else { 113 writeback(inst, state->mainPkt); --- 28 unchanged lines hidden (view full) --- 142 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 143 unsigned id) 144{ 145 cpu = cpu_ptr; 146 iewStage = iew_ptr; 147 148 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 149 | 107 iewStage->decrWb(inst->seqNum); 108 } else { 109 if (!state->noWB) { 110 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 111 !state->isLoad) { 112 writeback(inst, pkt); 113 } else { 114 writeback(inst, state->mainPkt); --- 28 unchanged lines hidden (view full) --- 143 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 144 unsigned id) 145{ 146 cpu = cpu_ptr; 147 iewStage = iew_ptr; 148 149 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 150 |
150 switchedOut = false; 151 152 cacheBlockMask = 0; 153 | |
154 lsq = lsq_ptr; 155 156 lsqID = id; 157 158 // Add 1 for the sentinel entry (they are circular queues). 159 LQEntries = maxLQEntries + 1; 160 SQEntries = maxSQEntries + 1; 161 162 loadQueue.resize(LQEntries); 163 storeQueue.resize(SQEntries); 164 165 depCheckShift = params->LSQDepCheckShift; 166 checkLoads = params->LSQCheckLoads; | 151 lsq = lsq_ptr; 152 153 lsqID = id; 154 155 // Add 1 for the sentinel entry (they are circular queues). 156 LQEntries = maxLQEntries + 1; 157 SQEntries = maxSQEntries + 1; 158 159 loadQueue.resize(LQEntries); 160 storeQueue.resize(SQEntries); 161 162 depCheckShift = params->LSQDepCheckShift; 163 checkLoads = params->LSQCheckLoads; |
164 cachePorts = params->cachePorts; 165 needsTSO = params->needsTSO; |
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167 | 166 |
167 resetState(); 168} 169 170 171template<class Impl> 172void 173LSQUnit<Impl>::resetState() 174{ 175 loads = stores = storesToWB = 0; 176 |
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168 loadHead = loadTail = 0; 169 170 storeHead = storeWBIdx = storeTail = 0; 171 172 usedPorts = 0; | 177 loadHead = loadTail = 0; 178 179 storeHead = storeWBIdx = storeTail = 0; 180 181 usedPorts = 0; |
173 cachePorts = params->cachePorts; | |
174 175 retryPkt = NULL; 176 memDepViolator = NULL; 177 178 blockedLoadSeqNum = 0; | 182 183 retryPkt = NULL; 184 memDepViolator = NULL; 185 186 blockedLoadSeqNum = 0; |
179 needsTSO = params->needsTSO; | 187 188 stalled = false; 189 isLoadBlocked = false; 190 loadBlockedHandled = false; 191 192 cacheBlockMask = 0; |
180} 181 182template<class Impl> 183std::string 184LSQUnit<Impl>::name() const 185{ 186 if (Impl::MaxThreads == 1) { 187 return iewStage->name() + ".lsq"; --- 65 unchanged lines hidden (view full) --- 253void 254LSQUnit<Impl>::clearSQ() 255{ 256 storeQueue.clear(); 257} 258 259template<class Impl> 260void | 193} 194 195template<class Impl> 196std::string 197LSQUnit<Impl>::name() const 198{ 199 if (Impl::MaxThreads == 1) { 200 return iewStage->name() + ".lsq"; --- 65 unchanged lines hidden (view full) --- 266void 267LSQUnit<Impl>::clearSQ() 268{ 269 storeQueue.clear(); 270} 271 272template<class Impl> 273void |
261LSQUnit<Impl>::switchOut() | 274LSQUnit<Impl>::drainSanityCheck() const |
262{ | 275{ |
263 switchedOut = true; 264 for (int i = 0; i < loadQueue.size(); ++i) { | 276 for (int i = 0; i < loadQueue.size(); ++i) |
265 assert(!loadQueue[i]); | 277 assert(!loadQueue[i]); |
266 loadQueue[i] = NULL; 267 } | |
268 269 assert(storesToWB == 0); | 278 279 assert(storesToWB == 0); |
280 assert(!retryPkt); |
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270} 271 272template<class Impl> 273void 274LSQUnit<Impl>::takeOverFrom() 275{ | 281} 282 283template<class Impl> 284void 285LSQUnit<Impl>::takeOverFrom() 286{ |
276 switchedOut = false; 277 loads = stores = storesToWB = 0; 278 279 loadHead = loadTail = 0; 280 281 storeHead = storeWBIdx = storeTail = 0; 282 283 usedPorts = 0; 284 285 memDepViolator = NULL; 286 287 blockedLoadSeqNum = 0; 288 289 stalled = false; 290 isLoadBlocked = false; 291 loadBlockedHandled = false; 292 293 // Just incase the memory system changed out from under us 294 cacheBlockMask = 0; | 287 resetState(); |
295} 296 297template<class Impl> 298void 299LSQUnit<Impl>::resizeLQ(unsigned size) 300{ 301 unsigned size_plus_sentinel = size + 1; 302 assert(size_plus_sentinel >= LQEntries); --- 990 unchanged lines hidden --- | 288} 289 290template<class Impl> 291void 292LSQUnit<Impl>::resizeLQ(unsigned size) 293{ 294 unsigned size_plus_sentinel = size + 1; 295 assert(size_plus_sentinel >= LQEntries); --- 990 unchanged lines hidden --- |