lsq_unit_impl.hh (8733:64a7bf8fa56c) lsq_unit_impl.hh (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include "arch/generic/debugfaults.hh"
45#include "arch/locked_mem.hh"
46#include "base/str.hh"
47#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include "arch/generic/debugfaults.hh"
45#include "arch/locked_mem.hh"
46#include "base/str.hh"
47#include "config/the_isa.hh"
48#include "cpu/checker/cpu.hh"
48#include "cpu/o3/lsq.hh"
49#include "cpu/o3/lsq_unit.hh"
50#include "debug/Activity.hh"
51#include "debug/IEW.hh"
52#include "debug/LSQUnit.hh"
53#include "mem/packet.hh"
54#include "mem/request.hh"
55
49#include "cpu/o3/lsq.hh"
50#include "cpu/o3/lsq_unit.hh"
51#include "debug/Activity.hh"
52#include "debug/IEW.hh"
53#include "debug/LSQUnit.hh"
54#include "mem/packet.hh"
55#include "mem/request.hh"
56
56#if USE_CHECKER
57#include "cpu/checker/cpu.hh"
58#endif
59
60template<class Impl>
61LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
62 LSQUnit *lsq_ptr)
63 : Event(Default_Pri, AutoDelete),
64 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
65{
66}
67

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866
867 if (!success) {
868 // Instantly complete this store.
869 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
870 "Instantly completing it.\n",
871 inst->seqNum);
872 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
873 cpu->schedule(wb, curTick() + 1);
57template<class Impl>
58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
59 LSQUnit *lsq_ptr)
60 : Event(Default_Pri, AutoDelete),
61 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
62{
63}
64

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863
864 if (!success) {
865 // Instantly complete this store.
866 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
867 "Instantly completing it.\n",
868 inst->seqNum);
869 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
870 cpu->schedule(wb, curTick() + 1);
874#if USE_CHECKER
875 // Make sure to set the LLSC data for verification
876 inst->reqToVerify->setExtraData(0);
877 inst->completeAcc(data_pkt);
878#endif
871 if (cpu->checker) {
872 // Make sure to set the LLSC data for verification
873 // if checker is loaded
874 inst->reqToVerify->setExtraData(0);
875 inst->completeAcc(data_pkt);
876 }
879 completeStore(storeWBIdx);
880 incrStIdx(storeWBIdx);
881 continue;
882 }
883 } else {
884 // Non-store conditionals do not need a writeback.
885 state->noWB = true;
886 }

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1078 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1079 }
1080
1081 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1082 // The store is basically completed at this time. This
1083 // only works so long as the checker doesn't try to
1084 // verify the value in memory for stores.
1085 storeQueue[storeWBIdx].inst->setCompleted();
877 completeStore(storeWBIdx);
878 incrStIdx(storeWBIdx);
879 continue;
880 }
881 } else {
882 // Non-store conditionals do not need a writeback.
883 state->noWB = true;
884 }

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1076 iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1077 }
1078
1079 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
1080 // The store is basically completed at this time. This
1081 // only works so long as the checker doesn't try to
1082 // verify the value in memory for stores.
1083 storeQueue[storeWBIdx].inst->setCompleted();
1086#if USE_CHECKER
1084
1087 if (cpu->checker) {
1088 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1089 }
1085 if (cpu->checker) {
1086 cpu->checker->verify(storeQueue[storeWBIdx].inst);
1087 }
1090#endif
1091 }
1092
1093 if (needsTSO) {
1094 storeInFlight = true;
1095 }
1096
1097 incrStIdx(storeWBIdx);
1098}

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1169
1170 if (needsTSO) {
1171 storeInFlight = false;
1172 }
1173
1174 // Tell the checker we've completed this instruction. Some stores
1175 // may get reported twice to the checker, but the checker can
1176 // handle that case.
1088 }
1089
1090 if (needsTSO) {
1091 storeInFlight = true;
1092 }
1093
1094 incrStIdx(storeWBIdx);
1095}

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1166
1167 if (needsTSO) {
1168 storeInFlight = false;
1169 }
1170
1171 // Tell the checker we've completed this instruction. Some stores
1172 // may get reported twice to the checker, but the checker can
1173 // handle that case.
1177#if USE_CHECKER
1178 if (cpu->checker) {
1179 cpu->checker->verify(storeQueue[store_idx].inst);
1180 }
1174 if (cpu->checker) {
1175 cpu->checker->verify(storeQueue[store_idx].inst);
1176 }
1181#endif
1182}
1183
1184template <class Impl>
1185bool
1186LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1187{
1188 if (!dcachePort->sendTiming(data_pkt)) {
1189 // Need to handle becoming blocked on a store.

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1178
1179template <class Impl>
1180bool
1181LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1182{
1183 if (!dcachePort->sendTiming(data_pkt)) {
1184 // Need to handle becoming blocked on a store.

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