lsq_unit_impl.hh (8272:82057507f2f9) lsq_unit_impl.hh (8481:818aea9960f5)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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711 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
712 assert(storeQueue[storeWBIdx].sreqLow);
713 assert(storeQueue[storeWBIdx].sreqHigh);
714 }
715
716 DynInstPtr inst = storeQueue[storeWBIdx].inst;
717
718 Request *req = storeQueue[storeWBIdx].req;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 702 unchanged lines hidden (view full) ---

711 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
712 assert(storeQueue[storeWBIdx].sreqLow);
713 assert(storeQueue[storeWBIdx].sreqHigh);
714 }
715
716 DynInstPtr inst = storeQueue[storeWBIdx].inst;
717
718 Request *req = storeQueue[storeWBIdx].req;
719 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
720 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
721
719 storeQueue[storeWBIdx].committed = true;
720
721 assert(!inst->memData);
722 inst->memData = new uint8_t[64];
723
724 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
725
726 MemCmd command =

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736
737 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
738
739 // Build a single data packet if the store isn't split.
740 data_pkt = new Packet(req, command, Packet::Broadcast);
741 data_pkt->dataStatic(inst->memData);
742 data_pkt->senderState = state;
743 } else {
722 storeQueue[storeWBIdx].committed = true;
723
724 assert(!inst->memData);
725 inst->memData = new uint8_t[64];
726
727 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
728
729 MemCmd command =

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739
740 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
741
742 // Build a single data packet if the store isn't split.
743 data_pkt = new Packet(req, command, Packet::Broadcast);
744 data_pkt->dataStatic(inst->memData);
745 data_pkt->senderState = state;
746 } else {
744 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
745 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
746
747 // Create two packets if the store is split in two.
748 data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
749 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
750
751 data_pkt->dataStatic(inst->memData);
752 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
753
754 data_pkt->senderState = state;

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789 incrStIdx(storeWBIdx);
790 continue;
791 }
792 } else {
793 // Non-store conditionals do not need a writeback.
794 state->noWB = true;
795 }
796
747 // Create two packets if the store is split in two.
748 data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
749 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
750
751 data_pkt->dataStatic(inst->memData);
752 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
753
754 data_pkt->senderState = state;

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789 incrStIdx(storeWBIdx);
790 continue;
791 }
792 } else {
793 // Non-store conditionals do not need a writeback.
794 state->noWB = true;
795 }
796
797 if (!sendStore(data_pkt)) {
797 bool split =
798 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
799
800 ThreadContext *thread = cpu->tcBase(lsqID);
801
802 if (req->isMmappedIpr()) {
803 assert(!inst->isStoreConditional());
804 TheISA::handleIprWrite(thread, data_pkt);
805 delete data_pkt;
806 if (split) {
807 assert(snd_data_pkt->req->isMmappedIpr());
808 TheISA::handleIprWrite(thread, snd_data_pkt);
809 delete snd_data_pkt;
810 delete sreqLow;
811 delete sreqHigh;
812 }
813 delete state;
814 delete req;
815 completeStore(storeWBIdx);
816 incrStIdx(storeWBIdx);
817 } else if (!sendStore(data_pkt)) {
798 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
799 "retry later\n",
800 inst->seqNum);
801
802 // Need to store the second packet, if split.
818 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
819 "retry later\n",
820 inst->seqNum);
821
822 // Need to store the second packet, if split.
803 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
823 if (split) {
804 state->pktToSend = true;
805 state->pendingPacket = snd_data_pkt;
806 }
807 } else {
808
809 // If split, try to send the second packet too
824 state->pktToSend = true;
825 state->pendingPacket = snd_data_pkt;
826 }
827 } else {
828
829 // If split, try to send the second packet too
810 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
830 if (split) {
811 assert(snd_data_pkt);
812
813 // Ensure there are enough ports to use.
814 if (usedPorts < cachePorts) {
815 ++usedPorts;
816 if (sendStore(snd_data_pkt)) {
817 storePostSend(snd_data_pkt);
818 } else {

--- 365 unchanged lines hidden --- 		831 assert(snd_data_pkt);
832
833 // Ensure there are enough ports to use.
834 if (usedPorts < cachePorts) {
835 ++usedPorts;
836 if (sendStore(snd_data_pkt)) {
837 storePostSend(snd_data_pkt);
838 } else {

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