lsq_unit_impl.hh (7848:cc5e64f8423f) lsq_unit_impl.hh (7852:07ba4754ae0a)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 76 unchanged lines hidden (view full) ---

85}
86
87template<class Impl>
88void
89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
90{
91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
92 DynInstPtr inst = state->inst;
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 76 unchanged lines hidden (view full) ---

85}
86
87template<class Impl>
88void
89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
90{
91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
92 DynInstPtr inst = state->inst;
93 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
93 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
95
96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
97
98 assert(!pkt->wasNacked());
99
100 // If this is a split access, wait until all packets are received.
101 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
102 delete pkt->req;

--- 1083 unchanged lines hidden --- 		95
96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
97
98 assert(!pkt->wasNacked());
99
100 // If this is a split access, wait until all packets are received.
101 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
102 delete pkt->req;

--- 1083 unchanged lines hidden ---