lsq_unit_impl.hh (6974:4d4903a3e7c5) lsq_unit_impl.hh (7597:063f160e8b50)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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434
435 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
436 inst->readPC(),inst->seqNum);
437
438 assert(!inst->isSquashed());
439
440 load_fault = inst->initiateAcc();
441
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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446
447 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
448 inst->readPC(),inst->seqNum);
449
450 assert(!inst->isSquashed());
451
452 load_fault = inst->initiateAcc();
453
442 // If the instruction faulted, then we need to send it along to commit
443 // without the instruction completing.
444 if (load_fault != NoFault) {
454 // If the instruction faulted or predicated false, then we need to send it
455 // along to commit without the instruction completing.
456 if (load_fault != NoFault || inst->readPredicate() == false) {
445 // Send this instruction to commit, also make sure iew stage
446 // realizes there is activity.
447 // Mark it as executed unless it is an uncached load that
448 // needs to hit the head of commit.
449 if (!(inst->hasRequest() && inst->uncacheable()) ||
450 inst->isAtCommit()) {
451 inst->setExecuted();
452 }

--- 696 unchanged lines hidden --- 		457 // Send this instruction to commit, also make sure iew stage
458 // realizes there is activity.
459 // Mark it as executed unless it is an uncached load that
460 // needs to hit the head of commit.
461 if (!(inst->hasRequest() && inst->uncacheable()) ||
462 inst->isAtCommit()) {
463 inst->setExecuted();
464 }

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