lsq_unit_impl.hh (4329:52057dbec096) lsq_unit_impl.hh (4332:548ef28989b8)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 631 unchanged lines hidden (view full) ---

640 DynInstPtr inst = storeQueue[storeWBIdx].inst;
641
642 Request *req = storeQueue[storeWBIdx].req;
643 storeQueue[storeWBIdx].committed = true;
644
645 assert(!inst->memData);
646 inst->memData = new uint8_t[64];
647
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 631 unchanged lines hidden (view full) ---

640 DynInstPtr inst = storeQueue[storeWBIdx].inst;
641
642 Request *req = storeQueue[storeWBIdx].req;
643 storeQueue[storeWBIdx].committed = true;
644
645 assert(!inst->memData);
646 inst->memData = new uint8_t[64];
647
648 TheISA::IntReg convertedData =
649 TheISA::htog(storeQueue[storeWBIdx].data);
648 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
650
649
651 //FIXME This is a hack to get SPARC working. It, along with endianness
652 //in the memory system in general, need to be straightened out more
653 //formally. The problem is that the data's endianness is swapped when
654 //it's in the 64 bit data field in the store queue. The data that you
655 //want won't start at the beginning of the field anymore unless it was
656 //a 64 bit access.
657 memcpy(inst->memData,
658 (uint8_t *)&convertedData +
659 (TheISA::ByteOrderDiffers ?
660 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
661 req->getSize());
662
663 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
664 Packet::Broadcast);
665 data_pkt->dataStatic(inst->memData);
666
667 LSQSenderState *state = new LSQSenderState;
668 state->isLoad = false;
669 state->idx = storeWBIdx;
670 state->inst = inst;

--- 378 unchanged lines hidden --- 		650 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
651 Packet::Broadcast);
652 data_pkt->dataStatic(inst->memData);
653
654 LSQSenderState *state = new LSQSenderState;
655 state->isLoad = false;
656 state->idx = storeWBIdx;
657 state->inst = inst;

--- 378 unchanged lines hidden ---