lsq_unit_impl.hh (4319:b8eae8c6afcc) lsq_unit_impl.hh (4326:a9277254c1e4)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 43 unchanged lines hidden (view full) ---

52
53template<class Impl>
54void
55LSQUnit<Impl>::WritebackEvent::process()
56{
57 if (!lsqPtr->isSwitchedOut()) {
58 lsqPtr->writeback(inst, pkt);
59 }
60
61 if (pkt->senderState)
62 delete pkt->senderState;
63
64 delete pkt->req;
65 delete pkt;
66}
67
68template<class Impl>
69const char *
70LSQUnit<Impl>::WritebackEvent::description()
71{
72 return "Store writeback event";

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80 DynInstPtr inst = state->inst;
81 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
82 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
83
84 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
85
86 if (isSwitchedOut() || inst->isSquashed()) {
87 iewStage->decrWb(inst->seqNum);
60 delete pkt;
61}
62
63template<class Impl>
64const char *
65LSQUnit<Impl>::WritebackEvent::description()
66{
67 return "Store writeback event";

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75 DynInstPtr inst = state->inst;
76 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
77 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
78
79 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
80
81 if (isSwitchedOut() || inst->isSquashed()) {
82 iewStage->decrWb(inst->seqNum);
83 delete state;
84 delete pkt->req;
85 delete pkt;
86 return;
88 } else {
89 if (!state->noWB) {
90 writeback(inst, pkt);
91 }
92
93 if (inst->isStore()) {
94 completeStore(state->idx);
95 }

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637 DynInstPtr inst = storeQueue[storeWBIdx].inst;
638
639 Request *req = storeQueue[storeWBIdx].req;
640 storeQueue[storeWBIdx].committed = true;
641
642 assert(!inst->memData);
643 inst->memData = new uint8_t[64];
644
87 } else {
88 if (!state->noWB) {
89 writeback(inst, pkt);
90 }
91
92 if (inst->isStore()) {
93 completeStore(state->idx);
94 }

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636 DynInstPtr inst = storeQueue[storeWBIdx].inst;
637
638 Request *req = storeQueue[storeWBIdx].req;
639 storeQueue[storeWBIdx].committed = true;
640
641 assert(!inst->memData);
642 inst->memData = new uint8_t[64];
643
645 TheISA::IntReg convertedData =
646 TheISA::htog(storeQueue[storeWBIdx].data);
644 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
647
645
648 //FIXME This is a hack to get SPARC working. It, along with endianness
649 //in the memory system in general, need to be straightened out more
650 //formally. The problem is that the data's endianness is swapped when
651 //it's in the 64 bit data field in the store queue. The data that you
652 //want won't start at the beginning of the field anymore unless it was
653 //a 64 bit access.
654 memcpy(inst->memData,
655 (uint8_t *)&convertedData +
656 (TheISA::ByteOrderDiffers ?
657 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
658 req->getSize());
659
660 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
661 Packet::Broadcast);
662 data_pkt->dataStatic(inst->memData);
663
664 LSQSenderState *state = new LSQSenderState;
665 state->isLoad = false;
666 state->idx = storeWBIdx;
667 state->inst = inst;

--- 378 unchanged lines hidden --- 		646 PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
647 Packet::Broadcast);
648 data_pkt->dataStatic(inst->memData);
649
650 LSQSenderState *state = new LSQSenderState;
651 state->isLoad = false;
652 state->idx = storeWBIdx;
653 state->inst = inst;

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