lsq_unit_impl.hh (3791:f1783bae1afe) lsq_unit_impl.hh (3797:9b58fa5ccaf5)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 587 unchanged lines hidden (view full) ---

596 storeQueue[storeWBIdx].committed = true;
597
598 assert(!inst->memData);
599 inst->memData = new uint8_t[64];
600
601 TheISA::IntReg convertedData =
602 TheISA::htog(storeQueue[storeWBIdx].data);
603
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 587 unchanged lines hidden (view full) ---

596 storeQueue[storeWBIdx].committed = true;
597
598 assert(!inst->memData);
599 inst->memData = new uint8_t[64];
600
601 TheISA::IntReg convertedData =
602 TheISA::htog(storeQueue[storeWBIdx].data);
603
604 memcpy(inst->memData, (uint8_t *)&convertedData,
605 req->getSize());
604 //FIXME This is a hack to get SPARC working. It, along with endianness
605 //in the memory system in general, need to be straightened out more
606 //formally. The problem is that the data's endianness is swapped when
607 //it's in the 64 bit data field in the store queue. The data that you
608 //want won't start at the beginning of the field anymore unless it was
609 //a 64 bit access.
610 memcpy(inst->memData,
611 (uint8_t *)&convertedData +
612 (TheISA::ByteOrderDiffers ?
613 (sizeof(TheISA::IntReg) - req->getSize()) : 0),
614 req->getSize());
606
607 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
608 data_pkt->dataStatic(inst->memData);
609
610 LSQSenderState *state = new LSQSenderState;
611 state->isLoad = false;
612 state->idx = storeWBIdx;
613 state->inst = inst;
614 data_pkt->senderState = state;
615
616 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
617 "to Addr:%#x, data:%#x [sn:%lli]\n",
618 storeWBIdx, inst->readPC(),
615
616 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
617 data_pkt->dataStatic(inst->memData);
618
619 LSQSenderState *state = new LSQSenderState;
620 state->isLoad = false;
621 state->idx = storeWBIdx;
622 state->inst = inst;
623 data_pkt->senderState = state;
624
625 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
626 "to Addr:%#x, data:%#x [sn:%lli]\n",
627 storeWBIdx, inst->readPC(),
619 req->getPaddr(), *(inst->memData),
628 req->getPaddr(), (int)*(inst->memData),
620 inst->seqNum);
621
622 // @todo: Remove this SC hack once the memory system handles it.
623 if (req->isLocked()) {
624 // Disable recording the result temporarily. Writing to
625 // misc regs normally updates the result, but this is not
626 // the desired behavior when handling store conditionals.
627 inst->recordResult = false;

--- 355 unchanged lines hidden --- 		629 inst->seqNum);
630
631 // @todo: Remove this SC hack once the memory system handles it.
632 if (req->isLocked()) {
633 // Disable recording the result temporarily. Writing to
634 // misc regs normally updates the result, but this is not
635 // the desired behavior when handling store conditionals.
636 inst->recordResult = false;

--- 355 unchanged lines hidden ---