lsq_unit_impl.hh (3492:20b28fd2cab5) lsq_unit_impl.hh (3594:e401993e0cbb)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
32#include "config/use_checker.hh"
33
34#include "cpu/o3/lsq.hh"
35#include "cpu/o3/lsq_unit.hh"
36#include "base/str.hh"
37#include "mem/packet.hh"
38#include "mem/request.hh"
39

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610 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
611 "to Addr:%#x, data:%#x [sn:%lli]\n",
612 storeWBIdx, inst->readPC(),
613 req->getPaddr(), *(inst->memData),
614 inst->seqNum);
615
616 // @todo: Remove this SC hack once the memory system handles it.
617 if (req->isLocked()) {
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40

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611 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
612 "to Addr:%#x, data:%#x [sn:%lli]\n",
613 storeWBIdx, inst->readPC(),
614 req->getPaddr(), *(inst->memData),
615 inst->seqNum);
616
617 // @todo: Remove this SC hack once the memory system handles it.
618 if (req->isLocked()) {
618 if (req->isUncacheable()) {
619 req->setScResult(2);
620 } else {
621 if (cpu->lockFlag) {
622 req->setScResult(1);
623 DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
624 inst->seqNum);
625 } else {
626 req->setScResult(0);
627 // Hack: Instantly complete this store.
628// completeDataAccess(data_pkt);
629 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
630 "Instantly completing it.\n",
631 inst->seqNum);
632 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
633 wb->schedule(curTick + 1);
634 delete state;
635 completeStore(storeWBIdx);
636 incrStIdx(storeWBIdx);
637 continue;
638 }
619 // Disable recording the result temporarily. Writing to
620 // misc regs normally updates the result, but this is not
621 // the desired behavior when handling store conditionals.
622 inst->recordResult = false;
623 bool success = TheISA::handleLockedWrite(inst.get(), req);
624 inst->recordResult = true;
625
626 if (!success) {
627 // Instantly complete this store.
628 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
629 "Instantly completing it.\n",
630 inst->seqNum);
631 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
632 wb->schedule(curTick + 1);
633 delete state;
634 completeStore(storeWBIdx);
635 incrStIdx(storeWBIdx);
636 continue;
639 }
640 } else {
641 // Non-store conditionals do not need a writeback.
642 state->noWB = true;
643 }
644
645 if (!dcachePort->sendTiming(data_pkt)) {
646 if (data_pkt->result == Packet::BadAddress) {

--- 333 unchanged lines hidden --- 		637 }
638 } else {
639 // Non-store conditionals do not need a writeback.
640 state->noWB = true;
641 }
642
643 if (!dcachePort->sendTiming(data_pkt)) {
644 if (data_pkt->result == Packet::BadAddress) {

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