lsq_unit_impl.hh (3230:e86a03911728) lsq_unit_impl.hh (3326:d9cc6bae9d77)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "arch/locked_mem.hh"
32#include "config/use_checker.hh"
33
34#include "cpu/o3/lsq.hh"
35#include "cpu/o3/lsq_unit.hh"
36#include "base/str.hh"
37#include "mem/packet.hh"
38#include "mem/request.hh"
39

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609 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
610 "to Addr:%#x, data:%#x [sn:%lli]\n",
611 storeWBIdx, inst->readPC(),
612 req->getPaddr(), *(inst->memData),
613 inst->seqNum);
614
615 // @todo: Remove this SC hack once the memory system handles it.
616 if (req->isLocked()) {
33#include "config/use_checker.hh"
34
35#include "cpu/o3/lsq.hh"
36#include "cpu/o3/lsq_unit.hh"
37#include "base/str.hh"
38#include "mem/packet.hh"
39#include "mem/request.hh"
40

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610 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
611 "to Addr:%#x, data:%#x [sn:%lli]\n",
612 storeWBIdx, inst->readPC(),
613 req->getPaddr(), *(inst->memData),
614 inst->seqNum);
615
616 // @todo: Remove this SC hack once the memory system handles it.
617 if (req->isLocked()) {
617 if (req->isUncacheable()) {
618 req->setScResult(2);
619 } else {
620 if (cpu->lockFlag) {
621 req->setScResult(1);
622 DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
623 inst->seqNum);
624 } else {
625 req->setScResult(0);
626 // Hack: Instantly complete this store.
627// completeDataAccess(data_pkt);
628 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
629 "Instantly completing it.\n",
630 inst->seqNum);
631 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
632 wb->schedule(curTick + 1);
633 delete state;
634 completeStore(storeWBIdx);
635 incrStIdx(storeWBIdx);
636 continue;
637 }
618 // Disable recording the result temporarily. Writing to
619 // misc regs normally updates the result, but this is not
620 // the desired behavior when handling store conditionals.
621 inst->recordResult = false;
622 bool success = TheISA::handleLockedWrite(inst.get(), req);
623 inst->recordResult = true;
624
625 if (!success) {
626 // Instantly complete this store.
627 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
628 "Instantly completing it.\n",
629 inst->seqNum);
630 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
631 wb->schedule(curTick + 1);
632 delete state;
633 completeStore(storeWBIdx);
634 incrStIdx(storeWBIdx);
635 continue;
638 }
639 } else {
640 // Non-store conditionals do not need a writeback.
641 state->noWB = true;
642 }
643
644 if (!dcachePort->sendTiming(data_pkt)) {
645 if (data_pkt->result == Packet::BadAddress) {

--- 333 unchanged lines hidden --- 		636 }
637 } else {
638 // Non-store conditionals do not need a writeback.
639 state->noWB = true;
640 }
641
642 if (!dcachePort->sendTiming(data_pkt)) {
643 if (data_pkt->result == Packet::BadAddress) {

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