lsq_unit_impl.hh (3221:669a04468c0d) lsq_unit_impl.hh (3230:e86a03911728)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 402 unchanged lines hidden (view full) ---

411
412 // If the instruction faulted, then we need to send it along to commit
413 // without the instruction completing.
414 if (load_fault != NoFault) {
415 // Send this instruction to commit, also make sure iew stage
416 // realizes there is activity.
417 // Mark it as executed unless it is an uncached load that
418 // needs to hit the head of commit.
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 402 unchanged lines hidden (view full) ---

411
412 // If the instruction faulted, then we need to send it along to commit
413 // without the instruction completing.
414 if (load_fault != NoFault) {
415 // Send this instruction to commit, also make sure iew stage
416 // realizes there is activity.
417 // Mark it as executed unless it is an uncached load that
418 // needs to hit the head of commit.
419 if (!(inst->req->getFlags() & UNCACHEABLE) || inst->isAtCommit()) {
419 if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
420 inst->setExecuted();
421 }
422 iewStage->instToCommit(inst);
423 iewStage->activityThisCycle();
424 }
425
426 return load_fault;
427}

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608
609 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
610 "to Addr:%#x, data:%#x [sn:%lli]\n",
611 storeWBIdx, inst->readPC(),
612 req->getPaddr(), *(inst->memData),
613 inst->seqNum);
614
615 // @todo: Remove this SC hack once the memory system handles it.
420 inst->setExecuted();
421 }
422 iewStage->instToCommit(inst);
423 iewStage->activityThisCycle();
424 }
425
426 return load_fault;
427}

--- 180 unchanged lines hidden (view full) ---

608
609 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
610 "to Addr:%#x, data:%#x [sn:%lli]\n",
611 storeWBIdx, inst->readPC(),
612 req->getPaddr(), *(inst->memData),
613 inst->seqNum);
614
615 // @todo: Remove this SC hack once the memory system handles it.
616 if (req->getFlags() & LOCKED) {
617 if (req->getFlags() & UNCACHEABLE) {
616 if (req->isLocked()) {
617 if (req->isUncacheable()) {
618 req->setScResult(2);
619 } else {
620 if (cpu->lockFlag) {
621 req->setScResult(1);
622 DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
623 inst->seqNum);
624 } else {
625 req->setScResult(0);

--- 353 unchanged lines hidden --- 		618 req->setScResult(2);
619 } else {
620 if (cpu->lockFlag) {
621 req->setScResult(1);
622 DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
623 inst->seqNum);
624 } else {
625 req->setScResult(0);

--- 353 unchanged lines hidden ---