lsq_unit_impl.hh (2820:7fde0b0f8f78) lsq_unit_impl.hh (2871:7ed5c9ef3eb6)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 168 unchanged lines hidden (view full) ---

177
178template<class Impl>
179void
180LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
181{
182 cpu = cpu_ptr;
183 dcachePort = new DcachePort(cpu, this);
184
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 168 unchanged lines hidden (view full) ---

177
178template<class Impl>
179void
180LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
181{
182 cpu = cpu_ptr;
183 dcachePort = new DcachePort(cpu, this);
184
185 Port *mem_dport = mem->getPort("");
186 dcachePort->setPeer(mem_dport);
187 mem_dport->setPeer(dcachePort);
188
189#if USE_CHECKER
190 if (cpu->checker) {
191 cpu->checker->setDcachePort(dcachePort);
192 }
193#endif
194}
195
196template<class Impl>

--- 791 unchanged lines hidden --- 		185#if USE_CHECKER
186 if (cpu->checker) {
187 cpu->checker->setDcachePort(dcachePort);
188 }
189#endif
190}
191
192template<class Impl>

--- 791 unchanged lines hidden ---