lsq_unit_impl.hh (2722:610b13e19da0) lsq_unit_impl.hh (2727:91e17c7ee622)
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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193 return iewStage->name() + ".lsq";
194 } else {
195 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
196 }
197}
198
199template<class Impl>
200void
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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193 return iewStage->name() + ".lsq";
194 } else {
195 return iewStage->name() + ".lsq.thread." + to_string(lsqID);
196 }
197}
198
199template<class Impl>
200void
201LSQUnit<Impl>::regStats()
202{
203 lsqForwLoads
204 .name(name() + ".forwLoads")
205 .desc("Number of loads that had data forwarded from stores");
206
207 invAddrLoads
208 .name(name() + ".invAddrLoads")
209 .desc("Number of loads ignored due to an invalid address");
210
211 lsqSquashedLoads
212 .name(name() + ".squashedLoads")
213 .desc("Number of loads squashed");
214
215 lsqIgnoredResponses
216 .name(name() + ".ignoredResponses")
217 .desc("Number of memory responses ignored because the instruction is squashed");
218
219 lsqSquashedStores
220 .name(name() + ".squashedStores")
221 .desc("Number of stores squashed");
222
223 invAddrSwpfs
224 .name(name() + ".invAddrSwpfs")
225 .desc("Number of software prefetches ignored due to an invalid address");
226
227 lsqBlockedLoads
228 .name(name() + ".blockedLoads")
229 .desc("Number of blocked loads due to partial load-store forwarding");
230
231 lsqRescheduledLoads
232 .name(name() + ".rescheduledLoads")
233 .desc("Number of loads that were rescheduled");
234
235 lsqCacheBlocked
236 .name(name() + ".cacheBlocked")
237 .desc("Number of times an access to memory failed due to the cache being blocked");
238}
239
240template<class Impl>
241void
201LSQUnit<Impl>::clearLQ()
202{
203 loadQueue.clear();
204}
205
206template<class Impl>
207void
208LSQUnit<Impl>::clearSQ()

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613 } else {
614 // Non-store conditionals do not need a writeback.
615 state->noWB = true;
616 }
617
618 if (!dcachePort->sendTiming(data_pkt)) {
619 // Need to handle becoming blocked on a store.
620 isStoreBlocked = true;
242LSQUnit<Impl>::clearLQ()
243{
244 loadQueue.clear();
245}
246
247template<class Impl>
248void
249LSQUnit<Impl>::clearSQ()

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654 } else {
655 // Non-store conditionals do not need a writeback.
656 state->noWB = true;
657 }
658
659 if (!dcachePort->sendTiming(data_pkt)) {
660 // Need to handle becoming blocked on a store.
661 isStoreBlocked = true;
621
662 ++lsqCacheBlocked;
622 assert(retryPkt == NULL);
623 retryPkt = data_pkt;
624 } else {
625 storePostSend(data_pkt);
626 }
627 }
628
629 // Not sure this should set it to 0.

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672 loadQueue[load_idx]->squashed = true;
673 loadQueue[load_idx] = NULL;
674 --loads;
675
676 // Inefficient!
677 loadTail = load_idx;
678
679 decrLdIdx(load_idx);
663 assert(retryPkt == NULL);
664 retryPkt = data_pkt;
665 } else {
666 storePostSend(data_pkt);
667 }
668 }
669
670 // Not sure this should set it to 0.

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713 loadQueue[load_idx]->squashed = true;
714 loadQueue[load_idx] = NULL;
715 --loads;
716
717 // Inefficient!
718 loadTail = load_idx;
719
720 decrLdIdx(load_idx);
721 ++lsqSquashedLoads;
680 }
681
682 if (isLoadBlocked) {
683 if (squashed_num < blockedLoadSeqNum) {
684 isLoadBlocked = false;
685 loadBlockedHandled = false;
686 blockedLoadSeqNum = 0;
687 }

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718
719 storeQueue[store_idx].req = NULL;
720 --stores;
721
722 // Inefficient!
723 storeTail = store_idx;
724
725 decrStIdx(store_idx);
722 }
723
724 if (isLoadBlocked) {
725 if (squashed_num < blockedLoadSeqNum) {
726 isLoadBlocked = false;
727 loadBlockedHandled = false;
728 blockedLoadSeqNum = 0;
729 }

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760
761 storeQueue[store_idx].req = NULL;
762 --stores;
763
764 // Inefficient!
765 storeTail = store_idx;
766
767 decrStIdx(store_idx);
768 ++lsqSquashedStores;
726 }
727}
728
729template <class Impl>
730void
731LSQUnit<Impl>::storePostSend(Packet *pkt)
732{
733 if (isStalled() &&

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777void
778LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
779{
780 iewStage->wakeCPU();
781
782 // Squashed instructions do not need to complete their access.
783 if (inst->isSquashed()) {
784 assert(!inst->isStore());
769 }
770}
771
772template <class Impl>
773void
774LSQUnit<Impl>::storePostSend(Packet *pkt)
775{
776 if (isStalled() &&

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820void
821LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
822{
823 iewStage->wakeCPU();
824
825 // Squashed instructions do not need to complete their access.
826 if (inst->isSquashed()) {
827 assert(!inst->isStore());
828 ++lsqIgnoredResponses;
785 return;
786 }
787
788 if (!inst->isExecuted()) {
789 inst->setExecuted();
790
791 // Complete access to copy data to proper place.
792 inst->completeAcc(pkt);

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853 assert(retryPkt != NULL);
854
855 if (dcachePort->sendTiming(retryPkt)) {
856 storePostSend(retryPkt);
857 retryPkt = NULL;
858 isStoreBlocked = false;
859 } else {
860 // Still blocked!
829 return;
830 }
831
832 if (!inst->isExecuted()) {
833 inst->setExecuted();
834
835 // Complete access to copy data to proper place.
836 inst->completeAcc(pkt);

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897 assert(retryPkt != NULL);
898
899 if (dcachePort->sendTiming(retryPkt)) {
900 storePostSend(retryPkt);
901 retryPkt = NULL;
902 isStoreBlocked = false;
903 } else {
904 // Still blocked!
905 ++lsqCacheBlocked;
861 }
862 } else if (isLoadBlocked) {
863 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
864 "no need to resend packet.\n");
865 } else {
866 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
867 }
868}

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907 } else if (isLoadBlocked) {
908 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
909 "no need to resend packet.\n");
910 } else {
911 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
912 }
913}

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