lsq_unit_impl.hh (13590:d7e018859709) lsq_unit_impl.hh (13652:45d94ac03a27)
1
2/*
3 * Copyright (c) 2010-2014, 2017-2018 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

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119
120 /* Notify the sender state that the access is complete (for ownership
121 * tracking). */
122 state->complete();
123
124 assert(!cpu->switchedOut());
125 if (!inst->isSquashed()) {
126 if (state->needWB) {
1
2/*
3 * Copyright (c) 2010-2014, 2017-2018 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

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119
120 /* Notify the sender state that the access is complete (for ownership
121 * tracking). */
122 state->complete();
123
124 assert(!cpu->switchedOut());
125 if (!inst->isSquashed()) {
126 if (state->needWB) {
127 // Only loads and store conditionals perform the writeback
127 // Only loads, store conditionals and atomics perform the writeback
128 // after receving the response from the memory
128 // after receving the response from the memory
129 assert(inst->isLoad() || inst->isStoreConditional());
129 assert(inst->isLoad() || inst->isStoreConditional() ||
130 inst->isAtomic());
130 writeback(inst, state->request()->mainPacket());
131 writeback(inst, state->request()->mainPacket());
131 if (inst->isStore()) {
132 if (inst->isStore() || inst->isAtomic()) {
132 auto ss = dynamic_cast<SQSenderState*>(state);
133 ss->writebackDone();
134 completeStore(ss->idx);
135 }
136 } else if (inst->isStore()) {
133 auto ss = dynamic_cast<SQSenderState*>(state);
134 ss->writebackDone();
135 completeStore(ss->idx);
136 }
137 } else if (inst->isStore()) {
138 // This is a regular store (i.e., not store conditionals and
139 // atomics), so it can complete without writing back
137 completeStore(dynamic_cast<SQSenderState*>(state)->idx);
138 }
139 }
140}
141
142template <class Impl>
143LSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
144 : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),

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269}
270
271template <class Impl>
272void
273LSQUnit<Impl>::insert(const DynInstPtr &inst)
274{
275 assert(inst->isMemRef());
276
140 completeStore(dynamic_cast<SQSenderState*>(state)->idx);
141 }
142 }
143}
144
145template <class Impl>
146LSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
147 : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),

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272}
273
274template <class Impl>
275void
276LSQUnit<Impl>::insert(const DynInstPtr &inst)
277{
278 assert(inst->isMemRef());
279
277 assert(inst->isLoad() || inst->isStore());
280 assert(inst->isLoad() || inst->isStore() || inst->isAtomic());
278
279 if (inst->isLoad()) {
280 insertLoad(inst);
281 } else {
282 insertStore(inst);
283 }
284
285 inst->setInLSQ();

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609 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
610 store_inst->pcState(), store_inst->seqNum);
611
612 return store_fault;
613 }
614
615 assert(store_fault == NoFault);
616
281
282 if (inst->isLoad()) {
283 insertLoad(inst);
284 } else {
285 insertStore(inst);
286 }
287
288 inst->setInLSQ();

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612 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
613 store_inst->pcState(), store_inst->seqNum);
614
615 return store_fault;
616 }
617
618 assert(store_fault == NoFault);
619
617 if (store_inst->isStoreConditional()) {
618 // Store conditionals need to set themselves as able to
620 if (store_inst->isStoreConditional() || store_inst->isAtomic()) {
621 // Store conditionals and Atomics need to set themselves as able to
619 // writeback if we haven't had a fault by here.
620 storeQueue[store_idx].canWB() = true;
621
622 ++storesToWB;
623 }
624
625 return checkViolations(loadIt, store_inst);
626

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746
747 if (req->senderState() == nullptr) {
748 SQSenderState *state = new SQSenderState(storeWBIt);
749 state->isLoad = false;
750 state->needWB = false;
751 state->inst = inst;
752
753 req->senderState(state);
622 // writeback if we haven't had a fault by here.
623 storeQueue[store_idx].canWB() = true;
624
625 ++storesToWB;
626 }
627
628 return checkViolations(loadIt, store_inst);
629

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749
750 if (req->senderState() == nullptr) {
751 SQSenderState *state = new SQSenderState(storeWBIt);
752 state->isLoad = false;
753 state->needWB = false;
754 state->inst = inst;
755
756 req->senderState(state);
754 if (inst->isStoreConditional()) {
755 /* Only store conditionals need a writeback. */
757 if (inst->isStoreConditional() || inst->isAtomic()) {
758 /* Only store conditionals and atomics need a writeback. */
756 state->needWB = true;
757 }
758 }
759 req->buildPackets();
760
761 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
762 "to Addr:%#x, data:%#x [sn:%lli]\n",
763 storeWBIt.idx(), inst->pcState(),

--- 350 unchanged lines hidden --- 		759 state->needWB = true;
760 }
761 }
762 req->buildPackets();
763
764 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
765 "to Addr:%#x, data:%#x [sn:%lli]\n",
766 storeWBIt.idx(), inst->pcState(),

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