lsq_unit_impl.hh (12749:223c83ed9979) lsq_unit_impl.hh (13429:a1e199fd8122)
1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 47 unchanged lines hidden (view full) ---

56#include "debug/Activity.hh"
57#include "debug/IEW.hh"
58#include "debug/LSQUnit.hh"
59#include "debug/O3PipeView.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63template<class Impl>
1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 47 unchanged lines hidden (view full) ---

56#include "debug/Activity.hh"
57#include "debug/IEW.hh"
58#include "debug/LSQUnit.hh"
59#include "debug/O3PipeView.hh"
60#include "mem/packet.hh"
61#include "mem/request.hh"
62
63template<class Impl>
64LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
65 LSQUnit *lsq_ptr)
64LSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst,
65 PacketPtr _pkt, LSQUnit *lsq_ptr)
66 : Event(Default_Pri, AutoDelete),
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
68{
69}
70
71template<class Impl>
72void
73LSQUnit<Impl>::WritebackEvent::process()

--- 260 unchanged lines hidden (view full) ---

334 SQEntries = size_plus_sentinel;
335 }
336
337 assert(SQEntries <= 256);
338}
339
340template <class Impl>
341void
66 : Event(Default_Pri, AutoDelete),
67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
68{
69}
70
71template<class Impl>
72void
73LSQUnit<Impl>::WritebackEvent::process()

--- 260 unchanged lines hidden (view full) ---

334 SQEntries = size_plus_sentinel;
335 }
336
337 assert(SQEntries <= 256);
338}
339
340template <class Impl>
341void
342LSQUnit::insert(DynInstPtr &inst)
342LSQUnit<Impl>::insert(const DynInstPtr &inst)
343{
344 assert(inst->isMemRef());
345
346 assert(inst->isLoad() || inst->isStore());
347
348 if (inst->isLoad()) {
349 insertLoad(inst);
350 } else {
351 insertStore(inst);
352 }
353
354 inst->setInLSQ();
355}
356
357template <class Impl>
358void
343{
344 assert(inst->isMemRef());
345
346 assert(inst->isLoad() || inst->isStore());
347
348 if (inst->isLoad()) {
349 insertLoad(inst);
350 } else {
351 insertStore(inst);
352 }
353
354 inst->setInLSQ();
355}
356
357template <class Impl>
358void
359LSQUnit::insertLoad(DynInstPtr &load_inst)
359LSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst)
360{
361 assert((loadTail + 1) % LQEntries != loadHead);
362 assert(loads < LQEntries);
363
364 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
365 load_inst->pcState(), loadTail, load_inst->seqNum);
366
367 load_inst->lqIdx = loadTail;

--- 8 unchanged lines hidden (view full) ---

376
377 incrLdIdx(loadTail);
378
379 ++loads;
380}
381
382template <class Impl>
383void
360{
361 assert((loadTail + 1) % LQEntries != loadHead);
362 assert(loads < LQEntries);
363
364 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
365 load_inst->pcState(), loadTail, load_inst->seqNum);
366
367 load_inst->lqIdx = loadTail;

--- 8 unchanged lines hidden (view full) ---

376
377 incrLdIdx(loadTail);
378
379 ++loads;
380}
381
382template <class Impl>
383void
384LSQUnit::insertStore(DynInstPtr &store_inst)
384LSQUnit<Impl>::insertStore(const DynInstPtr &store_inst)
385{
386 // Make sure it is not full before inserting an instruction.
387 assert((storeTail + 1) % SQEntries != storeHead);
388 assert(stores < SQEntries);
389
390 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
391 store_inst->pcState(), storeTail, store_inst->seqNum);
392

--- 127 unchanged lines hidden (view full) ---

520 }
521 incrLdIdx(load_idx);
522 }
523 return;
524}
525
526template <class Impl>
527Fault
385{
386 // Make sure it is not full before inserting an instruction.
387 assert((storeTail + 1) % SQEntries != storeHead);
388 assert(stores < SQEntries);
389
390 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
391 store_inst->pcState(), storeTail, store_inst->seqNum);
392

--- 127 unchanged lines hidden (view full) ---

520 }
521 incrLdIdx(load_idx);
522 }
523 return;
524}
525
526template <class Impl>
527Fault
528LSQUnit::checkViolations(int load_idx, DynInstPtr &inst)
528LSQUnit<Impl>::checkViolations(int load_idx, const DynInstPtr &inst)
529{
530 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
531 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
532
533 /** @todo in theory you only need to check an instruction that has executed
534 * however, there isn't a good way in the pipeline at the moment to check
535 * all instructions that will execute before the store writes back. Thus,
536 * like the implementation that came before it, we're overly conservative.

--- 63 unchanged lines hidden (view full) ---

600 return NoFault;
601}
602
603
604
605
606template <class Impl>
607Fault
529{
530 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
531 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
532
533 /** @todo in theory you only need to check an instruction that has executed
534 * however, there isn't a good way in the pipeline at the moment to check
535 * all instructions that will execute before the store writes back. Thus,
536 * like the implementation that came before it, we're overly conservative.

--- 63 unchanged lines hidden (view full) ---

600 return NoFault;
601}
602
603
604
605
606template <class Impl>
607Fault
608LSQUnit::executeLoad(DynInstPtr &inst)
608LSQUnit<Impl>::executeLoad(const DynInstPtr &inst)
609{
610 using namespace TheISA;
611 // Execute a specific load.
612 Fault load_fault = NoFault;
613
614 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
615 inst->pcState(), inst->seqNum);
616

--- 32 unchanged lines hidden (view full) ---

649 return checkViolations(load_idx, inst);
650 }
651
652 return load_fault;
653}
654
655template <class Impl>
656Fault
609{
610 using namespace TheISA;
611 // Execute a specific load.
612 Fault load_fault = NoFault;
613
614 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
615 inst->pcState(), inst->seqNum);
616

--- 32 unchanged lines hidden (view full) ---

649 return checkViolations(load_idx, inst);
650 }
651
652 return load_fault;
653}
654
655template <class Impl>
656Fault
657LSQUnit::executeStore(DynInstPtr &store_inst)
657LSQUnit<Impl>::executeStore(const DynInstPtr &store_inst)
658{
659 using namespace TheISA;
660 // Make sure that a store exists.
661 assert(stores != 0);
662
663 int store_idx = store_inst->sqIdx;
664
665 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",

--- 434 unchanged lines hidden (view full) ---

1100 storeInFlight = true;
1101 }
1102
1103 incrStIdx(storeWBIdx);
1104}
1105
1106template <class Impl>
1107void
658{
659 using namespace TheISA;
660 // Make sure that a store exists.
661 assert(stores != 0);
662
663 int store_idx = store_inst->sqIdx;
664
665 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",

--- 434 unchanged lines hidden (view full) ---

1100 storeInFlight = true;
1101 }
1102
1103 incrStIdx(storeWBIdx);
1104}
1105
1106template <class Impl>
1107void
1108LSQUnit::writeback(DynInstPtr &inst, PacketPtr pkt)
1108LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
1109{
1110 iewStage->wakeCPU();
1111
1112 // Squashed instructions do not need to complete their access.
1113 if (inst->isSquashed()) {
1114 assert(!inst->isStore());
1115 ++lsqIgnoredResponses;
1116 return;

--- 209 unchanged lines hidden --- 		1109{
1110 iewStage->wakeCPU();
1111
1112 // Squashed instructions do not need to complete their access.
1113 if (inst->isSquashed()) {
1114 assert(!inst->isStore());
1115 ++lsqIgnoredResponses;
1116 return;

--- 209 unchanged lines hidden ---