lsq_unit_impl.hh (12748:ae5ce8e42de7) lsq_unit_impl.hh (12749:223c83ed9979)
1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 65 unchanged lines hidden (view full) ---

74{
75 assert(!lsqPtr->cpu->switchedOut());
76
77 lsqPtr->writeback(inst, pkt);
78
79 if (pkt->senderState)
80 delete pkt->senderState;
81
1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 65 unchanged lines hidden (view full) ---

74{
75 assert(!lsqPtr->cpu->switchedOut());
76
77 lsqPtr->writeback(inst, pkt);
78
79 if (pkt->senderState)
80 delete pkt->senderState;
81
82 delete pkt->req;
83 delete pkt;
84}
85
86template<class Impl>
87const char *
88LSQUnit<Impl>::WritebackEvent::description() const
89{
90 return "Store writeback";

--- 37 unchanged lines hidden (view full) ---

128 }
129
130 if (inst->isStore()) {
131 completeStore(state->idx);
132 }
133 }
134
135 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
82 delete pkt;
83}
84
85template<class Impl>
86const char *
87LSQUnit<Impl>::WritebackEvent::description() const
88{
89 return "Store writeback";

--- 37 unchanged lines hidden (view full) ---

127 }
128
129 if (inst->isStore()) {
130 completeStore(state->idx);
131 }
132 }
133
134 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
136 delete state->mainPkt->req;
137 delete state->mainPkt;
138 }
139
140 pkt->req->setAccessLatency();
141 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
142
143 delete state;
144}

--- 681 unchanged lines hidden (view full) ---

826
827 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
828 assert(storeQueue[storeWBIdx].sreqLow);
829 assert(storeQueue[storeWBIdx].sreqHigh);
830 }
831
832 DynInstPtr inst = storeQueue[storeWBIdx].inst;
833
135 delete state->mainPkt;
136 }
137
138 pkt->req->setAccessLatency();
139 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
140
141 delete state;
142}

--- 681 unchanged lines hidden (view full) ---

824
825 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
826 assert(storeQueue[storeWBIdx].sreqLow);
827 assert(storeQueue[storeWBIdx].sreqHigh);
828 }
829
830 DynInstPtr inst = storeQueue[storeWBIdx].inst;
831
834 RequestPtr req = storeQueue[storeWBIdx].req;
835 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
836 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
832 RequestPtr &req = storeQueue[storeWBIdx].req;
833 const RequestPtr &sreqLow = storeQueue[storeWBIdx].sreqLow;
834 const RequestPtr &sreqHigh = storeQueue[storeWBIdx].sreqHigh;
837
838 storeQueue[storeWBIdx].committed = true;
839
840 assert(!inst->memData);
841 inst->memData = new uint8_t[req->getSize()];
842
843 if (storeQueue[storeWBIdx].isAllZeros)
844 memset(inst->memData, 0, req->getSize());

--- 24 unchanged lines hidden (view full) ---

869
870 data_pkt->senderState = state;
871 snd_data_pkt->senderState = state;
872
873 state->isSplit = true;
874 state->outstanding = 2;
875
876 // Can delete the main request now.
835
836 storeQueue[storeWBIdx].committed = true;
837
838 assert(!inst->memData);
839 inst->memData = new uint8_t[req->getSize()];
840
841 if (storeQueue[storeWBIdx].isAllZeros)
842 memset(inst->memData, 0, req->getSize());

--- 24 unchanged lines hidden (view full) ---

867
868 data_pkt->senderState = state;
869 snd_data_pkt->senderState = state;
870
871 state->isSplit = true;
872 state->outstanding = 2;
873
874 // Can delete the main request now.
877 delete req;
878 req = sreqLow;
879 }
880
881 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
882 "to Addr:%#x, data:%#x [sn:%lli]\n",
883 storeWBIdx, inst->pcState(),
884 req->getPaddr(), (int)*(inst->memData),
885 inst->seqNum);

--- 32 unchanged lines hidden (view full) ---

918 if (req->isMmappedIpr()) {
919 assert(!inst->isStoreConditional());
920 TheISA::handleIprWrite(thread, data_pkt);
921 delete data_pkt;
922 if (split) {
923 assert(snd_data_pkt->req->isMmappedIpr());
924 TheISA::handleIprWrite(thread, snd_data_pkt);
925 delete snd_data_pkt;
875 req = sreqLow;
876 }
877
878 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
879 "to Addr:%#x, data:%#x [sn:%lli]\n",
880 storeWBIdx, inst->pcState(),
881 req->getPaddr(), (int)*(inst->memData),
882 inst->seqNum);

--- 32 unchanged lines hidden (view full) ---

915 if (req->isMmappedIpr()) {
916 assert(!inst->isStoreConditional());
917 TheISA::handleIprWrite(thread, data_pkt);
918 delete data_pkt;
919 if (split) {
920 assert(snd_data_pkt->req->isMmappedIpr());
921 TheISA::handleIprWrite(thread, snd_data_pkt);
922 delete snd_data_pkt;
926 delete sreqLow;
927 delete sreqHigh;
928 }
929 delete state;
923 }
924 delete state;
930 delete req;
931 completeStore(storeWBIdx);
932 incrStIdx(storeWBIdx);
933 } else if (!sendStore(data_pkt)) {
934 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
935 "retry later\n",
936 inst->seqNum);
937
938 // Need to store the second packet, if split.

--- 117 unchanged lines hidden (view full) ---

1056 // Clear the smart pointer to make sure it is decremented.
1057 storeQueue[store_idx].inst->setSquashed();
1058 storeQueue[store_idx].inst = NULL;
1059 storeQueue[store_idx].canWB = 0;
1060
1061 // Must delete request now that it wasn't handed off to
1062 // memory. This is quite ugly. @todo: Figure out the proper
1063 // place to really handle request deletes.
925 completeStore(storeWBIdx);
926 incrStIdx(storeWBIdx);
927 } else if (!sendStore(data_pkt)) {
928 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
929 "retry later\n",
930 inst->seqNum);
931
932 // Need to store the second packet, if split.

--- 117 unchanged lines hidden (view full) ---

1050 // Clear the smart pointer to make sure it is decremented.
1051 storeQueue[store_idx].inst->setSquashed();
1052 storeQueue[store_idx].inst = NULL;
1053 storeQueue[store_idx].canWB = 0;
1054
1055 // Must delete request now that it wasn't handed off to
1056 // memory. This is quite ugly. @todo: Figure out the proper
1057 // place to really handle request deletes.
1064 delete storeQueue[store_idx].req;
1058 storeQueue[store_idx].req.reset();
1065 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1059 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
1066 delete storeQueue[store_idx].sreqLow;
1067 delete storeQueue[store_idx].sreqHigh;
1068
1069 storeQueue[store_idx].sreqLow = NULL;
1070 storeQueue[store_idx].sreqHigh = NULL;
1060 storeQueue[store_idx].sreqLow.reset();
1061 storeQueue[store_idx].sreqHigh.reset();
1071 }
1072
1062 }
1063
1073 storeQueue[store_idx].req = NULL;
1074 --stores;
1075
1076 // Inefficient!
1077 storeTail = store_idx;
1078
1079 decrStIdx(store_idx);
1080 ++lsqSquashedStores;
1081 }

--- 254 unchanged lines hidden --- 		1064 --stores;
1065
1066 // Inefficient!
1067 storeTail = store_idx;
1068
1069 decrStIdx(store_idx);
1070 ++lsqSquashedStores;
1071 }

--- 254 unchanged lines hidden ---