lsq_unit_impl.hh (12217:0a16f4c03c02) lsq_unit_impl.hh (12748:ae5ce8e42de7)
1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 817 unchanged lines hidden (view full) ---

826
827 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
828 assert(storeQueue[storeWBIdx].sreqLow);
829 assert(storeQueue[storeWBIdx].sreqHigh);
830 }
831
832 DynInstPtr inst = storeQueue[storeWBIdx].inst;
833
1
2/*
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 817 unchanged lines hidden (view full) ---

826
827 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
828 assert(storeQueue[storeWBIdx].sreqLow);
829 assert(storeQueue[storeWBIdx].sreqHigh);
830 }
831
832 DynInstPtr inst = storeQueue[storeWBIdx].inst;
833
834 Request *req = storeQueue[storeWBIdx].req;
834 RequestPtr req = storeQueue[storeWBIdx].req;
835 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
836 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
837
838 storeQueue[storeWBIdx].committed = true;
839
840 assert(!inst->memData);
841 inst->memData = new uint8_t[req->getSize()];
842

--- 493 unchanged lines hidden --- 		835 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
836 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
837
838 storeQueue[storeWBIdx].committed = true;
839
840 assert(!inst->memData);
841 inst->memData = new uint8_t[req->getSize()];
842

--- 493 unchanged lines hidden ---