lsq_unit_impl.hh (11780:9af039ea0c1e) lsq_unit_impl.hh (12216:70bb3ae0fbfc)
1
2/*
1
2/*
3 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license

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111 // If this is a split access, wait until all packets are received.
112 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
113 return;
114 }
115
116 assert(!cpu->switchedOut());
117 if (!inst->isSquashed()) {
118 if (!state->noWB) {
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license

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111 // If this is a split access, wait until all packets are received.
112 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
113 return;
114 }
115
116 assert(!cpu->switchedOut());
117 if (!inst->isSquashed()) {
118 if (!state->noWB) {
119 // Only loads and store conditionals perform the writeback
120 // after receving the response from the memory
121 assert(inst->isLoad() || inst->isStoreConditional());
119 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
120 !state->isLoad) {
121 writeback(inst, pkt);
122 } else {
123 writeback(inst, state->mainPkt);
124 }
125 }
126

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893
894 if (!success) {
895 // Instantly complete this store.
896 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
897 "Instantly completing it.\n",
898 inst->seqNum);
899 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
900 cpu->schedule(wb, curTick() + 1);
122 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
123 !state->isLoad) {
124 writeback(inst, pkt);
125 } else {
126 writeback(inst, state->mainPkt);
127 }
128 }
129

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896
897 if (!success) {
898 // Instantly complete this store.
899 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
900 "Instantly completing it.\n",
901 inst->seqNum);
902 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
903 cpu->schedule(wb, curTick() + 1);
901 if (cpu->checker) {
902 // Make sure to set the LLSC data for verification
903 // if checker is loaded
904 inst->reqToVerify->setExtraData(0);
905 inst->completeAcc(data_pkt);
906 }
907 completeStore(storeWBIdx);
908 incrStIdx(storeWBIdx);
909 continue;
910 }
911 } else {
912 // Non-store conditionals do not need a writeback.
913 state->noWB = true;
914 }

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1206
1207 if (needsTSO) {
1208 storeInFlight = false;
1209 }
1210
1211 // Tell the checker we've completed this instruction. Some stores
1212 // may get reported twice to the checker, but the checker can
1213 // handle that case.
904 completeStore(storeWBIdx);
905 incrStIdx(storeWBIdx);
906 continue;
907 }
908 } else {
909 // Non-store conditionals do not need a writeback.
910 state->noWB = true;
911 }

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1203
1204 if (needsTSO) {
1205 storeInFlight = false;
1206 }
1207
1208 // Tell the checker we've completed this instruction. Some stores
1209 // may get reported twice to the checker, but the checker can
1210 // handle that case.
1214 if (cpu->checker) {
1211
1212 // Store conditionals cannot be sent to the checker yet, they have
1213 // to update the misc registers first which should take place
1214 // when they commit
1215 if (cpu->checker && !storeQueue[store_idx].inst->isStoreConditional()) {
1215 cpu->checker->verify(storeQueue[store_idx].inst);
1216 }
1217}
1218
1219template <class Impl>
1220bool
1221LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1222{

--- 112 unchanged lines hidden --- 		1216 cpu->checker->verify(storeQueue[store_idx].inst);
1217 }
1218}
1219
1220template <class Impl>
1221bool
1222LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1223{

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