lsq_unit_impl.hh (11357:6668387fa488) lsq_unit_impl.hh (11780:9af039ea0c1e)
1
2/*
3 * Copyright (c) 2010-2014 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

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171 assert(LQEntries <= 256);
172 assert(SQEntries <= 256);
173
174 loadQueue.resize(LQEntries);
175 storeQueue.resize(SQEntries);
176
177 depCheckShift = params->LSQDepCheckShift;
178 checkLoads = params->LSQCheckLoads;
1
2/*
3 * Copyright (c) 2010-2014 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

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171 assert(LQEntries <= 256);
172 assert(SQEntries <= 256);
173
174 loadQueue.resize(LQEntries);
175 storeQueue.resize(SQEntries);
176
177 depCheckShift = params->LSQDepCheckShift;
178 checkLoads = params->LSQCheckLoads;
179 cachePorts = params->cachePorts;
179 cacheStorePorts = params->cacheStorePorts;
180 needsTSO = params->needsTSO;
181
182 resetState();
183}
184
185
186template<class Impl>
187void
188LSQUnit<Impl>::resetState()
189{
190 loads = stores = storesToWB = 0;
191
192 loadHead = loadTail = 0;
193
194 storeHead = storeWBIdx = storeTail = 0;
195
180 needsTSO = params->needsTSO;
181
182 resetState();
183}
184
185
186template<class Impl>
187void
188LSQUnit<Impl>::resetState()
189{
190 loads = stores = storesToWB = 0;
191
192 loadHead = loadTail = 0;
193
194 storeHead = storeWBIdx = storeTail = 0;
195
196 usedPorts = 0;
196 usedStorePorts = 0;
197
198 retryPkt = NULL;
199 memDepViolator = NULL;
200
201 stalled = false;
202
203 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
204}

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787 writebackPendingStore();
788 }
789
790 while (storesToWB > 0 &&
791 storeWBIdx != storeTail &&
792 storeQueue[storeWBIdx].inst &&
793 storeQueue[storeWBIdx].canWB &&
794 ((!needsTSO) || (!storeInFlight)) &&
197
198 retryPkt = NULL;
199 memDepViolator = NULL;
200
201 stalled = false;
202
203 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
204}

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787 writebackPendingStore();
788 }
789
790 while (storesToWB > 0 &&
791 storeWBIdx != storeTail &&
792 storeQueue[storeWBIdx].inst &&
793 storeQueue[storeWBIdx].canWB &&
794 ((!needsTSO) || (!storeInFlight)) &&
795 usedPorts < cachePorts) {
795 usedStorePorts < cacheStorePorts) {
796
797 if (isStoreBlocked) {
798 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
799 " is blocked!\n");
800 break;
801 }
802
803 // Store didn't write any data so no need to write it back to
804 // memory.
805 if (storeQueue[storeWBIdx].size == 0) {
806 completeStore(storeWBIdx);
807
808 incrStIdx(storeWBIdx);
809
810 continue;
811 }
812
796
797 if (isStoreBlocked) {
798 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
799 " is blocked!\n");
800 break;
801 }
802
803 // Store didn't write any data so no need to write it back to
804 // memory.
805 if (storeQueue[storeWBIdx].size == 0) {
806 completeStore(storeWBIdx);
807
808 incrStIdx(storeWBIdx);
809
810 continue;
811 }
812
813 ++usedPorts;
813 ++usedStorePorts;
814
815 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
816 incrStIdx(storeWBIdx);
817
818 continue;
819 }
820
821 assert(storeQueue[storeWBIdx].req);

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945 }
946 } else {
947
948 // If split, try to send the second packet too
949 if (split) {
950 assert(snd_data_pkt);
951
952 // Ensure there are enough ports to use.
814
815 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
816 incrStIdx(storeWBIdx);
817
818 continue;
819 }
820
821 assert(storeQueue[storeWBIdx].req);

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945 }
946 } else {
947
948 // If split, try to send the second packet too
949 if (split) {
950 assert(snd_data_pkt);
951
952 // Ensure there are enough ports to use.
953 if (usedPorts < cachePorts) {
954 ++usedPorts;
953 if (usedStorePorts < cacheStorePorts) {
954 ++usedStorePorts;
955 if (sendStore(snd_data_pkt)) {
956 storePostSend(snd_data_pkt);
957 } else {
958 DPRINTF(IEW, "D-Cache became blocked when writing"
959 " [sn:%lli] second packet, will retry later\n",
960 inst->seqNum);
961 }
962 } else {

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970
971 // Not a split store.
972 storePostSend(data_pkt);
973 }
974 }
975 }
976
977 // Not sure this should set it to 0.
955 if (sendStore(snd_data_pkt)) {
956 storePostSend(snd_data_pkt);
957 } else {
958 DPRINTF(IEW, "D-Cache became blocked when writing"
959 " [sn:%lli] second packet, will retry later\n",
960 inst->seqNum);
961 }
962 } else {

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970
971 // Not a split store.
972 storePostSend(data_pkt);
973 }
974 }
975 }
976
977 // Not sure this should set it to 0.
978 usedPorts = 0;
978 usedStorePorts = 0;
979
980 assert(stores >= 0 && storesToWB >= 0);
981}
982
983/*template <class Impl>
984void
985LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
986{

--- 348 unchanged lines hidden --- 		979
980 assert(stores >= 0 && storesToWB >= 0);
981}
982
983/*template <class Impl>
984void
985LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
986{

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