lsq_unit_impl.hh (10474:799c8ee4ecba) lsq_unit_impl.hh (10573:3b405d11d6dc)
1
2/*
3 * Copyright (c) 2010-2014 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

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100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
101
102 if (state->cacheBlocked) {
103 // This is the first half of a previous split load,
104 // where the 2nd half blocked, ignore this response
105 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
106 "blocked split load recieved. Ignoring.\n", inst->seqNum);
107 delete state;
1
2/*
3 * Copyright (c) 2010-2014 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual

--- 91 unchanged lines hidden (view full) ---

100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
101
102 if (state->cacheBlocked) {
103 // This is the first half of a previous split load,
104 // where the 2nd half blocked, ignore this response
105 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
106 "blocked split load recieved. Ignoring.\n", inst->seqNum);
107 delete state;
108 delete pkt->req;
109 delete pkt;
110 return;
111 }
112
113 // If this is a split access, wait until all packets are received.
114 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
108 return;
109 }
110
111 // If this is a split access, wait until all packets are received.
112 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
115 delete pkt->req;
116 delete pkt;
117 return;
118 }
119
120 assert(!cpu->switchedOut());
121 if (!inst->isSquashed()) {
122 if (!state->noWB) {
123 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
124 !state->isLoad) {

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137 delete state->mainPkt->req;
138 delete state->mainPkt;
139 }
140
141 pkt->req->setAccessLatency();
142 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
143
144 delete state;
113 return;
114 }
115
116 assert(!cpu->switchedOut());
117 if (!inst->isSquashed()) {
118 if (!state->noWB) {
119 if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
120 !state->isLoad) {

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133 delete state->mainPkt->req;
134 delete state->mainPkt;
135 }
136
137 pkt->req->setAccessLatency();
138 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
139
140 delete state;
145 delete pkt->req;
146 delete pkt;
147}
148
149template <class Impl>
150LSQUnit<Impl>::LSQUnit()
151 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
152 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false)
153{
154}

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142
143template <class Impl>
144LSQUnit<Impl>::LSQUnit()
145 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
146 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false)
147{
148}

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