lsq_unit_impl.hh (10327:5b6279635c49) lsq_unit_impl.hh (10333:6be8945d226b)
1
2/*
1
2/*
3 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2010-2014 ARM Limited
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license

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94void
95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
96{
97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
98 DynInstPtr inst = state->inst;
99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
101
4 * Copyright (c) 2013 Advanced Micro Devices, Inc.
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license

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94void
95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
96{
97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
98 DynInstPtr inst = state->inst;
99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
101
102 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
102 if (state->cacheBlocked) {
103 // This is the first half of a previous split load,
104 // where the 2nd half blocked, ignore this response
105 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
106 "blocked split load recieved. Ignoring.\n", inst->seqNum);
107 delete state;
108 delete pkt->req;
109 delete pkt;
110 return;
111 }
103
104 // If this is a split access, wait until all packets are received.
105 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
106 delete pkt->req;
107 delete pkt;
108 return;
109 }
110

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135 delete state;
136 delete pkt->req;
137 delete pkt;
138}
139
140template <class Impl>
141LSQUnit<Impl>::LSQUnit()
142 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
112
113 // If this is a split access, wait until all packets are received.
114 if (TheISA::HasUnalignedMemAcc && !state->complete()) {
115 delete pkt->req;
116 delete pkt;
117 return;
118 }
119

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144 delete state;
145 delete pkt->req;
146 delete pkt;
147}
148
149template <class Impl>
150LSQUnit<Impl>::LSQUnit()
151 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
143 isStoreBlocked(false), isLoadBlocked(false),
144 loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
152 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false)
145{
146}
147
148template<class Impl>
149void
150LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
151 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
152 unsigned id)

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190
191 storeHead = storeWBIdx = storeTail = 0;
192
193 usedPorts = 0;
194
195 retryPkt = NULL;
196 memDepViolator = NULL;
197
153{
154}
155
156template<class Impl>
157void
158LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
159 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
160 unsigned id)

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198
199 storeHead = storeWBIdx = storeTail = 0;
200
201 usedPorts = 0;
202
203 retryPkt = NULL;
204 memDepViolator = NULL;
205
198 blockedLoadSeqNum = 0;
199
200 stalled = false;
206 stalled = false;
201 isLoadBlocked = false;
202 loadBlockedHandled = false;
203
204 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
205}
206
207template<class Impl>
208std::string
209LSQUnit<Impl>::name() const
210{

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627 inst->seqNum,
628 (load_fault != NoFault ? "fault" : "predication"));
629 if (!(inst->hasRequest() && inst->uncacheable()) ||
630 inst->isAtCommit()) {
631 inst->setExecuted();
632 }
633 iewStage->instToCommit(inst);
634 iewStage->activityThisCycle();
207
208 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
209}
210
211template<class Impl>
212std::string
213LSQUnit<Impl>::name() const
214{

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631 inst->seqNum,
632 (load_fault != NoFault ? "fault" : "predication"));
633 if (!(inst->hasRequest() && inst->uncacheable()) ||
634 inst->isAtCommit()) {
635 inst->setExecuted();
636 }
637 iewStage->instToCommit(inst);
638 iewStage->activityThisCycle();
635 } else if (!loadBlocked()) {
639 } else {
636 assert(inst->effAddrValid());
637 int load_idx = inst->lqIdx;
638 incrLdIdx(load_idx);
639
640 if (checkLoads)
641 return checkViolations(load_idx, inst);
642 }
643

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782
783 while (storesToWB > 0 &&
784 storeWBIdx != storeTail &&
785 storeQueue[storeWBIdx].inst &&
786 storeQueue[storeWBIdx].canWB &&
787 ((!needsTSO) || (!storeInFlight)) &&
788 usedPorts < cachePorts) {
789
640 assert(inst->effAddrValid());
641 int load_idx = inst->lqIdx;
642 incrLdIdx(load_idx);
643
644 if (checkLoads)
645 return checkViolations(load_idx, inst);
646 }
647

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786
787 while (storesToWB > 0 &&
788 storeWBIdx != storeTail &&
789 storeQueue[storeWBIdx].inst &&
790 storeQueue[storeWBIdx].canWB &&
791 ((!needsTSO) || (!storeInFlight)) &&
792 usedPorts < cachePorts) {
793
790 if (isStoreBlocked || lsq->cacheBlocked()) {
794 if (isStoreBlocked) {
791 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
792 " is blocked!\n");
793 break;
794 }
795
796 // Store didn't write any data so no need to write it back to
797 // memory.
798 if (storeQueue[storeWBIdx].size == 0) {

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1019
1020 // Inefficient!
1021 loadTail = load_idx;
1022
1023 decrLdIdx(load_idx);
1024 ++lsqSquashedLoads;
1025 }
1026
795 DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
796 " is blocked!\n");
797 break;
798 }
799
800 // Store didn't write any data so no need to write it back to
801 // memory.
802 if (storeQueue[storeWBIdx].size == 0) {

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1023
1024 // Inefficient!
1025 loadTail = load_idx;
1026
1027 decrLdIdx(load_idx);
1028 ++lsqSquashedLoads;
1029 }
1030
1027 if (isLoadBlocked) {
1028 if (squashed_num < blockedLoadSeqNum) {
1029 isLoadBlocked = false;
1030 loadBlockedHandled = false;
1031 blockedLoadSeqNum = 0;
1032 }
1033 }
1034
1035 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
1036 memDepViolator = NULL;
1037 }
1038
1039 int store_idx = storeTail;
1040 decrStIdx(store_idx);
1041
1042 while (stores != 0 &&

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1213LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1214{
1215 if (!dcachePort->sendTimingReq(data_pkt)) {
1216 // Need to handle becoming blocked on a store.
1217 isStoreBlocked = true;
1218 ++lsqCacheBlocked;
1219 assert(retryPkt == NULL);
1220 retryPkt = data_pkt;
1031 if (memDepViolator && squashed_num < memDepViolator->seqNum) {
1032 memDepViolator = NULL;
1033 }
1034
1035 int store_idx = storeTail;
1036 decrStIdx(store_idx);
1037
1038 while (stores != 0 &&

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1209LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1210{
1211 if (!dcachePort->sendTimingReq(data_pkt)) {
1212 // Need to handle becoming blocked on a store.
1213 isStoreBlocked = true;
1214 ++lsqCacheBlocked;
1215 assert(retryPkt == NULL);
1216 retryPkt = data_pkt;
1221 lsq->setRetryTid(lsqID);
1222 return false;
1223 }
1224 return true;
1225}
1226
1227template <class Impl>
1228void
1229LSQUnit<Impl>::recvRetry()

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1239 // Don't finish the store unless this is the last packet.
1240 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1241 state->pendingPacket == retryPkt) {
1242 state->pktToSend = false;
1243 storePostSend(retryPkt);
1244 }
1245 retryPkt = NULL;
1246 isStoreBlocked = false;
1217 return false;
1218 }
1219 return true;
1220}
1221
1222template <class Impl>
1223void
1224LSQUnit<Impl>::recvRetry()

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1234 // Don't finish the store unless this is the last packet.
1235 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
1236 state->pendingPacket == retryPkt) {
1237 state->pktToSend = false;
1238 storePostSend(retryPkt);
1239 }
1240 retryPkt = NULL;
1241 isStoreBlocked = false;
1247 lsq->setRetryTid(InvalidThreadID);
1248
1249 // Send any outstanding packet.
1250 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1251 assert(state->pendingPacket);
1252 if (sendStore(state->pendingPacket)) {
1253 storePostSend(state->pendingPacket);
1254 }
1255 }
1256 } else {
1257 // Still blocked!
1258 ++lsqCacheBlocked;
1242
1243 // Send any outstanding packet.
1244 if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1245 assert(state->pendingPacket);
1246 if (sendStore(state->pendingPacket)) {
1247 storePostSend(state->pendingPacket);
1248 }
1249 }
1250 } else {
1251 // Still blocked!
1252 ++lsqCacheBlocked;
1259 lsq->setRetryTid(lsqID);
1260 }
1253 }
1261 } else if (isLoadBlocked) {
1262 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
1263 "no need to resend packet.\n");
1264 } else {
1265 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
1266 }
1267}
1268
1269template <class Impl>
1270inline void
1271LSQUnit<Impl>::incrStIdx(int &store_idx) const
1272{
1273 if (++store_idx >= SQEntries)

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1255}
1256
1257template <class Impl>
1258inline void
1259LSQUnit<Impl>::incrStIdx(int &store_idx) const
1260{
1261 if (++store_idx >= SQEntries)

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