lsq_unit_impl.hh (10030:b531e328342d) lsq_unit_impl.hh (10031:79d034cd6ba3)
1
2/*
3 * Copyright (c) 2010-2013 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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811
812 Request *req = storeQueue[storeWBIdx].req;
813 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
814 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
815
816 storeQueue[storeWBIdx].committed = true;
817
818 assert(!inst->memData);
1
2/*
3 * Copyright (c) 2010-2013 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 802 unchanged lines hidden (view full) ---

811
812 Request *req = storeQueue[storeWBIdx].req;
813 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
814 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
815
816 storeQueue[storeWBIdx].committed = true;
817
818 assert(!inst->memData);
819 inst->memData = new uint8_t[64];
819 inst->memData = new uint8_t[req->getSize()];
820
820
821 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
821 if (storeQueue[storeWBIdx].isAllZeros)
822 memset(inst->memData, 0, req->getSize());
823 else
824 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
822
823 MemCmd command =
824 req->isSwap() ? MemCmd::SwapReq :
825 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
826 PacketPtr data_pkt;
827 PacketPtr snd_data_pkt = NULL;
828
829 LSQSenderState *state = new LSQSenderState;

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826 MemCmd command =
827 req->isSwap() ? MemCmd::SwapReq :
828 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
829 PacketPtr data_pkt;
830 PacketPtr snd_data_pkt = NULL;
831
832 LSQSenderState *state = new LSQSenderState;

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